UART

Question

Hi, 
 I am using 21835-SOM board. I found that the serial port cannot communicate properly. 
 Please help me check the code. 
 
 Regards, UARTDMAMode.rar 
 Bingo

NandiniC · Accepted Answer

Hi Bingo, 
 Please find the attached example code where the buffer is placed in L2 memory. Please ensure that the cache management API is properly configured and the buffers are aligned to cache line boundaries when the cache is enabled. 
 6012.UART_DMA_Autobaud_SC835_SHARCFX_Core1.zip 
 The ADI_CACHE_MANAGEMENT macro defined in the "adi_pdma_config_SC8xx.h" file enables/disables cache management by the driver. 
 Aligning buffer memory to cache line boundaries ensures that cache maintenance operations apply to the buffer memory alone, and not operate on unrelated data that may inadvertently share memory space on that cache line. This may not be an issue for most applications, but it can cause problems if adjoining, misaligned memory is also being accessed or written off-core, possibly by DMA or by another processor core. 
 Regarding "Where can the cache settings be modified?" >> In order to configure cacheable and non-cacheable ranges, or otherwise change the cacheability settings of specific regions of memory, use the Startup Code/LSP Add-in to configure the cache settings for each memory segment. The settings are accessed by double-clicking on a memory segment to edit it, then clicking the Edit button next to "Access Properties" to change the MPU settings for the segment. 
 For more information, please refer the below CCES help path. CrossCore&reg; Embedded Studio 3.0.1 > SHARC&reg;-FX Development Tools Documentation > CrossCore Embedded Studio SHARC+ to SHARC-FX Migration Guide > Configuring cache settings on SHARC-FX 
 Regards, Nandini C)

SLA Status	Assignee	Support Status
SLA Closed. Missed after 936 hours		Closed

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