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UART

Thread Summary

The user is experiencing issues with UART communication in DMA mode on the ADSP-21835-SOM board, while core mode works correctly. The support engineer is simulating the issue and will provide further assistance. The user confirmed the hardware is functioning normally and provided test steps, terminal configurations, and register views for both modes.
AI Generated Content
Category: Software
Product Number: ADSP-21835
Software Version: CCES3.0.2

Hi,

I am using 21835-SOM board.I found that the serial port cannot communicate properly.

Please help me check the code.

Regards,UARTDMAMode.rar

Bingo

Parents Reply Children
  • Hi Bingo,

    We are checking this internally and will get back to you as soon as possible.

    Regards,
    Nandini C

  • Hi,

    May I ask if there has been any progress?

    Regards,

    Bingo

  • Hi,

    Apologies for the delay caused.

    We were able to simulate your issue on our end; we are checking and will get back to you as soon as possible.

    Regards,
    Nandini C

  • Hi,

    Please refer the attached example demonstrates the usage of baud rate detection automatically using “UART DMA” mode to scan the keyboard alphabets and send them onto a Terminal emulator such as TeraTerm.UART_DMA_Autobaud_SC835_SHARCFX_Core1.zip

    Please open a serial terminal application (for example PuTTY or TeraTerm) and configure a serial connection to the COM port with the settings as shown below:

    Bits Per second = Set any baud rate, range between 110 to 115200 bps
    Data bits = 8
    Parity = None
    Stop bits = 1
    Flow Control = None
    And follow the below steps:

    1. Open a terminal emulating tool such as tera term on PC and set the baud rate at which communication needs to be established.
    2. Run the example and enter "@" in the terminal emulator window so that the example can detect the baud rate and it will be displayed on the console window as "Detected Baudrate is xx"
    3. Any key pressed through keyboard will be displayed on the console window and to exit from this program press "Enter".

    Please run this example and let us know if any assistance is required.

    Regards,
    Nandini C

  • Hi,

    Why must the receive buffer be placed in the L1 RAM?Does this have to do with the cache settings?

    Where can the cache settings be modified?

    Regards,

    Bingo

  • Hi Bingo,

    Please find the attached example code where the buffer is placed in L2 memory. Please ensure that the cache management API is properly configured and the buffers are aligned to cache line boundaries when the cache is enabled.

    6012.UART_DMA_Autobaud_SC835_SHARCFX_Core1.zip

    The ADI_CACHE_MANAGEMENT macro defined in the "adi_pdma_config_SC8xx.h" file enables/disables cache management by the driver.

    Aligning buffer memory to cache line boundaries ensures that cache maintenance operations apply to the buffer memory alone, and not operate on unrelated data that may inadvertently share memory space on that cache line. This may not be an issue for most applications, but it can cause problems if adjoining, misaligned memory is also being accessed or written off-core, possibly by DMA or by another processor core.

    Regarding "Where can the cache settings be modified?"
    >> In order to configure cacheable and non-cacheable ranges, or otherwise change the cacheability settings of specific regions of memory, use the Startup Code/LSP Add-in to configure the cache settings for each memory segment. The settings are accessed by double-clicking on a memory segment to edit it, then clicking the Edit button next to "Access Properties" to change the MPU settings for the segment.

    For more information, please refer the below CCES help path.
    CrossCore® Embedded Studio 3.0.1 > SHARC®-FX Development Tools Documentation > CrossCore Embedded Studio SHARC+ to SHARC-FX Migration Guide > Configuring cache settings on SHARC-FX

    Regards,
    Nandini C

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