Want to know about Intrinsic optimization techniques

Hi Monika,

Thank you for your inquiry.

We are looking into this case. We will get back to you.

Best Regards,
Santhakumari.V

Hi Santhakumari, 

Thank you for your response. Awaiting for your reply. 

Thanks, 

Monika

Hi, santha.vijay , 

Do you have any update regarding this query? 

Thanks, 

Monika 

Hi Monika,

Apologies. I missed this thread. Vector Registers are not available for ADSP-SC594 processor. It is being supported from SHARC-FX processor only.

For more information, please refer to the below Ezone thread which might be helpful.
ez.analog.com/.../524024

Best Regards,
Santhakumari.V

Hi santha.vijay , 

Thanks for your information. 

I have gone through the SHARC FX core and its features. I didn't find the PRM, May I know is there any programming reference manual available for sharc fx to know about vector registers handling in details and ISA of the sharc Fx core?

If there are any examples codes available for vectorization handling in sharc fx , please provide us that might be useful for us. 

Thanks, 

Monika V

Hi santha.vijay , 

Do you have any update regarding this ?

Thanks,

Monika V

Hi Monika, 

We are checking with our Internal Development team. We will get back once we get a response from them.

Regards,
Santhakumari.V

All SHARC-FX related manuals are present in the following directory in CCES installation :

<Installation path​>\analog\cces\3.0.x\Xtensa\Docs

As a starting point, you can refer to the file "index.html" to get an understanding of the different manuals present in the below directory.

<Installation path​>\analog\cces\3.0.x\Xtensa\Docs\index.html

You can also refer to the "fusionJ6_ug.pdf" which explains about vectorization present in the below path:

<Installation path​>\analog\cces\3.0.x\Xtensa\Docs\fusionJ6_ug.pdf

Hope this helps.

Hi santha.vijay 

Thanks for the response. I will check as per your suggestions.

Thanks, 

Monika V