How to access L3 memory from the ARM core without passing via the data cache on the ADSP-SC594?

Hello.
Thank you for your prompt reply.

The following ARM core side code modifications and SHARC core side code additions allowed each other to access in the L3 memory data (range:0xB8000000-0xBFFFFFFF).

ARM core side
/system/linker/apt.c
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const adi_mmu_AbstractPageEntry _adi_mmu_absPageTable[] =
{
.....
//{ 0xA0000000u, 0xBFFFFFFFu, ADI_MMU_WB_CACHED }, /* 512MB DDR-A */
{ 0xA0000000u, 0xB7FFFFFFu, ADI_MMU_WB_CACHED }, /* 384MB DDR-A */
{ 0xB8000000u, 0xBFFFFFFFu, ADI_MMU_RW_UNCACHED }, /* 128MB DDR-A */
.....
};
-----------------------------------------------------------------------------------

SHARC core side
-----------------------------------------------------------------------------------
adiCacheStatus cache_stat;
cache_stat = adi_cache_set_range((void *)0xB8000000u,
(void *)0xBFFFFFFFu,
adi_cache_rr5,
adi_cache_noncacheable_range);
-----------------------------------------------------------------------------------

In consideration of exclusive access, the following code was inserted before and after accessing these areas.

ARM core side
-----------------------------------------------------------------------------------
uint32_t excl_addr = 0xB8000000u;
uint32_t excl_stat;
uint32_t excl_ret;

(before)
do
{
__asm volatile ("ldrex %0, [%1]" : "=r"(excl_stat) : "r" (excl_addr) : "memory);
} while (excl_stat != 0u);
excl_stat = 1u;
do
{
__asm volatile ("strex %0, %2, [%1]" : "=&r" (excl_ret) : "r" (excl_addr), "r" (excl_stat) : "memory");
} while (excl_ret != 0u);

(after)
do
{
__asm volatile ("ldrex %0, [%1]" : "=r"(excl_stat) : "r" (excl_addr) : "memory);
} while (excl_stat != 1u);
excl_stat = 0u;
do
{
__asm volatile ("strex %0, %2, [%1]" : "=&r" (excl_ret) : "r" (excl_addr), "r" (excl_stat) : "memory");
} while (excl_ret != 0u);
-----------------------------------------------------------------------------------

SHARC core side
-----------------------------------------------------------------------------------
uint32_t excl_addr = 0xB8000000u;
uint32_t excl_stat;
int excl_ret;

(before)
do
{
excl_stat = load_exclusive_32((unsigned volatile int *)excl_addr, &excl_ret);
} ((excl_ret != 0) && (excl_stat != 0u));
excl_stat = 1u;
do
{
excl_ret = store_exclusive_32(excl_stat, (unsigned volatile int *)excl_addr);
} (excl_ret != 0);

(after)
do
{
excl_stat = load_exclusive_32((unsigned volatile int *)excl_addr, &excl_ret);
} ((excl_ret != 0) && (excl_stat != 1u));
excl_stat = 0u;
do
{
excl_ret = store_exclusive_32(excl_stat, (unsigned volatile int *)excl_addr);
} (excl_ret != 0);
-----------------------------------------------------------------------------------

Hi,

Thanks for the update and glad to know that your issue is resolved.

Please let us know, if you need any further assistance.

Regards.
Nandini C