port B falling edge interrupt

Hi,

We understand that you are configuring PB_15 as an input. Please be aware that all GPIO pins default to input mode after a reset.
However, the input drivers are not enabled by default. To enable the GPIO input drivers, you will need to set the appropriate bits in the input enable register (PORT_INEN).Unfortunately, we could not find this configuration in the code you provided.

Additionally, in the line "*pREG_PINT0_ASSIGN = 0x00008100;", you are attempting to write to a Not Writable bit.

We recommend changing this to *pREG_PINT0_ASSIGN = 0x00000100; and trying again.

Regards,
Nandini C

Hi Nandini C,

Thank you for your response. 

I forgot to put in the initial port B code.  I am aware of the DIR and the INEN register. 

*pREG_PORTB_FER_SET = 0x0003; 
*pREG_PORTB_MUX |= PB0_PB1_TWI_1;

*pREG_PORTB_DIR_SET = 0x0090; 

*pREG_PORTB_INEN_SET = 0x8340; 

*pREG_PORTB_DATA_SET = 0x0090; //

On your comment:

Additionally, in the line "*pREG_PINT0_ASSIGN = 0x00008100;", you are attempting to write to a Not Writable bit.

I tried this and it still did not hop into the interrupt. 

Can you please elaborate on the Not Writeable bit that you were mentioning? I have to mention that the chapter for the GPIO to be part of the PINTx mechanism is vague in the HRM.  Since Port A or Port B can sharer PINT0 how does one configure as such?  So when I was dealing with the 21569, there was a lot of try and see if it works.  I want to mention again that this set of code did work for the 21569. 

Thank you and looking forward if there are other things to try. 

Hi Nandini C,

Thank you for your response. 

I forgot to put in the initial port B code.  I am aware of the DIR and the INEN register. 

*pREG_PORTB_FER_SET = 0x0003; 
*pREG_PORTB_MUX |= PB0_PB1_TWI_1;

*pREG_PORTB_DIR_SET = 0x0090; 

*pREG_PORTB_INEN_SET = 0x8340; 

*pREG_PORTB_DATA_SET = 0x0090; //

On your comment:

Additionally, in the line "*pREG_PINT0_ASSIGN = 0x00008100;", you are attempting to write to a Not Writable bit.

I tried this and it still did not hop into the interrupt. 

Can you please elaborate on the Not Writeable bit that you were mentioning? I have to mention that the chapter for the GPIO to be part of the PINTx mechanism is vague in the HRM.  Since Port A or Port B can sharer PINT0 how does one configure as such?  So when I was dealing with the 21569, there was a lot of try and see if it works.  I want to mention again that this set of code did work for the 21569. 

Thank you and looking forward if there are other things to try. 

Hi,

Regarding interrupt issue, we are checking on this in ADSP-21593 and will get back to you.

Regarding >> Can you please elaborate on the Not Writeable bit that you were mentioning?
>> The "Not Writable" bit in registers typically refers to a specific bit or flag in a register that indicates whether the register can be written to or not.
If the Not Writable bit (NW) is set, any attempts to write to the register will be ignored or may trigger an error. This bits should remain unchanged during normal operation.
Please find the below screenshot for reference.

I have to mention that the chapter for the GPIO to be part of the PINTx mechanism is vague in the HRM. Since Port A or Port B can sharer PINT0 how does one configure as such?
>> Below image can be referred as PINTx Block Diagram. The ports are subdivided into two 8-pin half ports, with lower(PxL) and upper(PxH) half 8-bit units. The lower half units of eight pins can be forwarded to either byte 0 or byte 2 of either associated PINTx block. Upper half units can be forwarded to either byte 1 or byte 3 of the pin interrupts blocks, without further restrictions.

As per the HRM, When you select PORTA and PORTB --> PA refers to PORTA and PB refers to PORTB in PINT0
When you select PORTB and PORTC --> PB refers to PORTB and PC refers to PORTC in PINT1

Now, let's consider a scenario where you want to configure an interrupt for Port B pin 15 (PB15). You can choose either PINT0 or PINT1, and let's assume you've selected PINT0 (using PB as your reference). If you select BYTE1 (PBH) for PB15, the corresponding pin interrupt unmask bit you need to select is PIQ15. Similarly, if you choose BYTE3 (PBH), the appropriate unmask bit will be PIQ31.

For your quick reference, PINTx register combination is given below.

PINT0:
BYTE3 = PA.H(Port A) or PB.H(Port B)
BYTE2 = PA.L(Port A) or PB.L(Port B)
BYTE1 = PA.H(Port A) or PB.H(Port B)
BYTE0 = PA.L(Port A) or PB.L(Port B)

PINT1:
BYTE3 = PB.H(Port B) or PC.H(Port C)
BYTE2 = PB.L(Port B) or PC.L(Port C)
BYTE1 = PB.H(Port B) or PC.H(Port C)
BYTE0 = PB.L(Port B) or PC.L(Port C)

Regards,
Nandini.C

Hi,

We have checked with configurations listed below, and it is working fine in EV-21593-SOM.
  *pREG_PORTB_FER_CLR = BITM_PORT_FER_CLR_PX15 ;      
  *pREG_PORTB_DIR_CLR = BITM_PORT_DIR_CLR_PX15 ;      
  *pREG_PORTB_INEN_SET = BITM_PORT_INEN_SET_PX15 ;    
  *pREG_PINT0_ASSIGN = BITM_PINT_ASSIGN_B1MAP ;        
  *pREG_PINT0_MSK_SET = BITM_PINT_MSK_SET_PIQ15;      
  *pREG_PINT0_EDGE_SET = BITM_PINT_EDGE_SET_PIQ15;
  *pREG_PINT0_INV_SET = BITM_PINT_INV_SET_PIQ15;
If you want interrupts to trigger on falling edges, you can use the PINT_INV_SET register to invert the polarity (i.e., the PINTx block generates the interrupt request when the signal goes from high to low).

We suspect this may be causing the issue. Please change this to PINT_INV_CLR or check whether your input changes from low to high.

Regards,
Nandini C