DDR3 issues with ADSP-SC598 on custom hardware, DMA access is not working, CORE access is working

Hi Andrew,

Could you please provide the following details to assist you further?
1. While running the DDR sweep test in DMA mode, is there any error bit set in the DMA register?
2. Are you experiencing the issue with a specific clock configuration?
3. Did you modified the DDR configuration based on your DDR3 memory (IS43TR16256B-125KBL)? If it is, please share the DDR register configurations.
4. Could you share an image of your console showing the addresses with incorrect data?

Additionally, please verify that the SPU register is configured according to "Table 40-11: Write-Protect Register and Secure Peripheral Number(n)" in the ADSP-SC598 hardware reference manual, which can be found here:
www.analog.com/.../adsp-sc595-sc596-sc598-hrm.pdf

We hope you have referred the DDR3 connection in the EV-SC598-SOM schematic diagram and have implemented the DDR3 connection on your custom board. The link to the EV-SC598-SOM schematic is provided below:
www.analog.com/.../ev-sc598-som-schematic.pdf

Regards,
Nandini

Hi Nandini,

Thanks for your help. I think the SPU registers are ok considering I run the same code on the SOM dev board and all tests pass. Is this a correct assumption?

1. There are no error bits set in the DMA_STAT register. I compared this to what gets set on the SOM dev board and it matches exactly.

2. I set the clocks to match what is on the SOM dev board:

Core Clock is 1GHz

SYSCLK is 500 MHz

DCLK is 800 MHz

SCLK0 is 125 MHz

SCLK1 is 333.33 MHz

3. I have tried changing different parts of the DDR configuration, but from what I can tell the default configuration for the SOM dev board should work without any modification. The SOM dev board uses a very similar DDR3L chip and runs at 800 MHz: IS43TR16256BL-107MBL. Our DDR3 chip is IS43TR16256B-125KBL

Here are the DDR settings I am currently using to test:

#define CFG0_REG_DDR_DLLCTLCFG 0x0cf00622ul
#define CFG0_REG_DMC_MR2MR3 0x00180004ul
#define CFG0_REG_DMC_CTL_VALUE 0x08004a05ul
#define CFG0_REG_DMC_MRMR1 0x0d7000c0ul
#define CFG0_REG_DMC_TR0_VALUE 0x4271cb6bul
#define CFG0_REG_DMC_TR1_VALUE 0x60D01860ul
#define CFG0_REG_DMC_TR2_VALUE 0x00450620ul
#define CFG0_REG_DMC_ZQCTL_0 0x00785A64ul
#define CFG0_REG_DMC_ZQCTL_1 0x00000000ul
#define CFG0_REG_DMC_ZQCTL_2 0x70000000ul

4. See image. Also including an excerpt from the console here:

drive.google.com/.../view

CORE_ACCESS
Test Word size = 1 byte
Data pattern = All A
Test Passed...

CORE_ACCESS
Test Word size = 1 byte
Data pattern = All 5
Test Passed...

CORE_ACCESS
Test Word size = 1 byte
Data pattern = INCREMENTAL
Test Passed...

CORE_ACCESS
Test Word size = 1 byte
Data pattern = RANDOM
Test Passed...

CORE_ACCESS
Test Word size = 1 byte
Data pattern = ALL_BITS_TOGGLING
Test Passed...

DMA_ACCESS
Test Word size = 1 byte
Data pattern = All A

Failure at DMC address=0x80000000, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000002, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000003, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000100, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000102, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000103, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000200, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000202, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000203, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000300, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000302, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000303, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000400, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000402, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000403, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000500, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000502, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000503, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000600, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000602, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000603, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000700, expected data=0xaa, read data=0x80

Failure at DMC address=0x80000702, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000703, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000800, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000802, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000803, expected data=0xaa, read data=0xa

Failure at DMC address=0x80000900, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000902, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000903, expected data=0xaa, read data=0xa

Andrew

Hello again,

I was able to make a little bit of progress on this issue since I last posted. I did a test where I run the DDR3 clock at 400 MHz and it works, all tests pass and I am able to load my program into DDR3 memory successfully. I set the DDR config to the default from the spreadsheet in the EE443 zip for 400 MHz. Here are the settings that work at 400 MHz DDR3 clock

//400 MHz
#define CFG0_REG_DDR_DLLCTLCFG 0x06f00622ul
#define CFG0_REG_DMC_MR2MR3 0x00180004ul
#define CFG0_REG_DMC_CTL_VALUE 0x00004a05ul
#define CFG0_REG_DMC_MRMR1 0x057000c0ul
#define CFG0_REG_DMC_TR0_VALUE 0x4140e646ul
#define CFG0_REG_DMC_TR1_VALUE 0x40680c30ul
#define CFG0_REG_DMC_TR2_VALUE 0x00330410ul
#define CFG0_REG_DMC_ZQCTL_0 0x00785A64ul
#define CFG0_REG_DMC_ZQCTL_1 0x00000000ul
#define CFG0_REG_DMC_ZQCTL_2 0x70000000ul

So to summarize, it is working with a 400 MHz clock but not at the full speed of 800 MHz like on the SOM dev board. What are some next steps you can recommend to see why it is not working at 800 MHz?

Further updates: I realized I had the data cache enabled, so that is why the CORE access was passing. If I disable the cache, then both the CORE and DMA access fail the same way.

Hi Andrew,

We have checked your DMC configuration and it seems fine.

To assist you more effectively, please contact us in private support via processor.support@analog.com email address with your custom board schematic diagram and kindly include the link to this Ezone thread in your message.

Regards,
Nandini C

Hi Andrew and NandiniC,

I have the same issue with a custom board SC598 board and using the IS43TR16256B-125KBL and wonder if you could help.

I have the sweep test program completing ok on the EV-SC598-SOM board.

On my custom board the test fails on the first CORE ACCESS test.

CORE_ACCESS
Test Word size = 1 byte
Data pattern = All A

Failure at DMC address=0x80000000, expected data=0xaa, read data=0xff

Failure at DMC address=0x80000001, expected data=0xaa, read data=0xff

Failure at DMC address=0x80000002, expected data=0xaa, read data=0xff

Failure at DMC address=0x80000003, expected data=0xaa, read data=0xff

Failure at DMC address=0x80000004, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000005, expected data=0xaa, read data=0x0

Failure at DMC address=0x80000006, expected data=0xaa, read data=0xff

Failure at DMC address=0x80000007, expected data=0xaa, read data=0xff

The core test was ok until like Andrew I turned off the cache.
I used the #defines Andrew used for the 400MHz operation but still unable to get it to work.

//400 MHz
#define CFG0_REG_DDR_DLLCTLCFG 0x06f00622ul
#define CFG0_REG_DMC_MR2MR3 0x00180004ul
#define CFG0_REG_DMC_CTL_VALUE 0x00004a05ul
#define CFG0_REG_DMC_MRMR1 0x057000c0ul
#define CFG0_REG_DMC_TR0_VALUE 0x4140e646ul
#define CFG0_REG_DMC_TR1_VALUE 0x40680c30ul
#define CFG0_REG_DMC_TR2_VALUE 0x00330410ul
#define CFG0_REG_DMC_ZQCTL_0 0x00785A64ul
#define CFG0_REG_DMC_ZQCTL_1 0x00000000ul
#define CFG0_REG_DMC_ZQCTL_2 0x70000000ul

My question is did you have to change any of the settings other than in main.h ?
such as the DDRClockTimePeriod in main.c or any of the settings in adi_dmc_config_generator.h

when debugging did you need preloader such as ezkitSC598W_preload_core1.dxe ?

did you ever get your custom board to work with 800MHz ?

Greatly appreciate any help. Many thanks

Alan

Hi Alan,

We have not yet gotten our board to work running the DDR3 clock at 800 MHz. Anything faster than 450 MHz will not work for us. We made some hardware changes to actively terminate the lines from the ADSP-SC598 to the DDR3 memory, and hope that will fix the issue. Our next rev of the board is supposed to arrive from the factory in a few weeks, I will update this thread if the hardware changes solve the issue.

We did have to make more changes, mostly CGU and CDU settings to change the clock speeds. Our processor uses an input clock of 24 MHz instead of 25 like on the SOM board so we have the clocks routed a little differently than on the SOM board. If your clocks are mostly the same you can just change CGU2_DSEL from 2 to 4 to make the DDR3 clock 400 MHz instead of 800 MHz. This is the divider that is used by default for the DDR3 memory: 25MHz * 64 / 4 = 400 MHz, and is defined in adi_pwr_SC598_family_1GHz_config.h

Andrew

Also I was not using a preloader project to run the code. The preloader does a lot of the same clock routing setup and DDR3 memory configuration that is done in this memory sweep program.

Hi Andrew,

Thank you so much for your quick response and very helpful information.  The sweep program now works at 400MHz which at least proves a lot on our custom board.  Now to figure out how to get it work at 800MHz.  It will be very interesting to hear if your modifications to the hardware work.  We used the same active termination as used on the SOM but that hasn't seemed to help so maybe its a layout issue.  I'll keep you updated on our progress.

Alan

Hi Alan,

Please refer to the "ADSP-SC595/SC596/SC598 Programming Guidelines for Dynamic Memory Controller" EE-Note available in the below link. It helps you to configure the DDR based on your requirement.
https://www.analog.com/media/en/technical-documentation/application-notes/ee-443.pdf

The main purpose of these pre-load files is to set up clocks and DMC settings so that the debugger is able to load the user’s application to external memory. External memory needs to be configured appropriately before applications can be loaded. When the application boots, this is done through initcodes; when the application is loaded to target using the debugger, this can be done by the IDE automatically using preload code.

To create the preload file for your custom board please refer to the "Creating Preload and Initialization Code with Customized CGU and DMC Settings" section in the EE-443 Note.

Regards,
Nandini.C