L1 / L2 cache access speed

Hi,

We would suggest you to refer the Application note "EE-412" ADSP-2156x SHARC+ Processor System Optimization Techniques, which discusses about the different memory region and cache memory. 
https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.pdf

Also, we would suggest you to download the associated zip file using the below link https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.zip

Regards,

Nandini C

Hi NandiniC, thank you for the information, I have read the AN but I was not able to identify for example how many extra cycles takes the access to L2 and L3 compared to L1, I know that there are many features that may influence this (word size, caches for instruction/data/program enabled, program/data memory access in one cycle, stalls, SIMD, etc.) The information I would like to understand is for example: if the access to L1 takes 1 cycle (CCLK), the average cycles to access L2 is 3 cycles (CCLK cycles), L3 takes 6 cycles (CCLK cycles). Is there any other document I could check?

Thanks,

Alfonso

Hi,

Generally, L1 is single cycle access and L2/L3 are multiple cycle access. For L2, any write that is less than 32-bit to an ECC-enabled SRAM bank is implemented as a read-followed-by-write and requires three cycles to complete (two cycles for the read, one cycle for the write).

When performing simultaneous core and DMA accesses to the same L2 memory bank, read and write priority control registers can be used to increase DMA throughput. If both the core and the DMA engine access the same bank, the best access rate that DMA can achieve is one 64-bit access every three SYSCLK cycles during the conflict period.

We have a simple code in our repository that tests read and write times for all three memories. This project is for ADSP-SC573. Could you please take this as an example and try change to ADSP-21569 to test the access cycles. Alternatives to measure the memory access would be to use the timer.h or cycle.h library. With the timer.h the actual elapsed time can be measured and with the cycle.h you get additional information for the clock cycle like the average.ADSP_SC573_MemoryAccessTime.zip

Please refer the path "CrossCore® Embedded Studio 2.12.0 > Blackfin® Development Tools Documentation > C/C++ Compiler and Library Manual for Blackfin® Processors > DSP Run-Time Library > DSP Run-Time Library Guide".

Regards,
Nandini C