EMAC

Hi,

Please note, the DMA in the EMAC module attempts to read a descriptor only if the tail pointer is different from the base pointer or current pointer. It is recommended to have a descriptor ring with a length that can accommodate at least two complete packets received by the MAC. Otherwise, the performance of the DMA is impacted greatly because of the unavailability of the descriptors. In such situations, the receive FIFO in the MTL becomes full and starts dropping packets.

Please refer the "Receive Descriptor" section(Pg. No:30-54) from EMAC chapter of the ADSP-SC598 HRM from the below link.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-sc595-sc596-sc598-hrm.pdf

You can also refer to the "EMAC" examples from ADSP-SC598 BSP.

Download the BSP of ADSP-SC598 from the attached .zip file

After installation, you can navigate the example from the below mentioned installation path.
path: \Analog Devices\EV-SC59x_EZ-KIT-Rel3.0.0\EV-SC59x_EZ-KIT\Examples\drivers\emac

Also, please share whether you are trying to achieve Normal descriptors or Context descriptors along with screenshot of the registers.

Regards,
Nandini C

ADI_EV-SC59x_EZ-KIT-Rel3.0.0.exe.zip

hi，

How to determine if the EMAC Tx (Transmit) and RX (Receive) DMA (Direct Memory Access) transmission is suspended?

Hi,

EMAC Tx (Transmit) and RX (Receive) DMA (Direct Memory Access) transmission is suspended can be determined by using the "Transmit Buffer Unavailable(EMAC_DMA[n]_STAT.TBU)" register bit and "Receive Buffer Unavailable( EMAC_DMA[n]_STAT.RBU)" register bit.

EMAC_DMA[n]_STAT.RBU : This bit signifies that the application controls the next descriptor in the receive list, preventing the DMA from accessing it. The Rx process is suspended.

EMAC_DMA[n]_STAT.TBU : This bit indicates that the application controls the next descriptor in the transmit list, preventing the DMA from accessing it. Transmission is suspended.

We would suggest you refer the section "DMA Channel n Status Register" [Page No:30–275] in ADSP-SC598 Hardware reference Manual from the below link,
https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-sc595-sc596-sc598-hrm.pdf

Also, you can refer to the "Normal Interrupt Summary" and "Abnormal Interrupt Summary" register bit from the above linked HRM.

Regards,
Nandini C

Hi,

hrm pg.1893 states "The receive DMA transfers data to a buffer until the buffer is full or the end of packet is received from the MTL. When the FD bit of a descriptor is set, the amount of valid data in a buffer is accurately indicated by the buffer size field (programmed in the EMAC_DMA[n]_RXCTL registers) minus the data buffer pointer offset. " But EMACPhyLoopback example does not consider this point, should this point be considered in usage?

Hi,
This query has been deleted before, so I opened a new discussion. Please answer my question, thank you.

Hi,

>> EMACPhyLoopback example does not consider this point, should this point be considered in usage.
Please note buffer size calculation is handled by the driver. The buffer length for the payload is set by the driver through the EMAC_DMA[n]_RXCTL.RBSZ_X_0 and EMAC_DMA[n]_RXCTL.RBSZ_13_Y fields.

In this loopback example it demonstrates the data sent from the MAC to PHY over Tx bus is loopedback inside the PHY and sent back to the MAC over Rx bus.

You can find packet size information in the status of the Receive Normal Descriptor (RDES3 Write-Back Format). Bits 14-0 represent the packet length, indicating the byte size of the received packet transferred to system memory (including CRC) under "emac_desc_rx."

We would suggest you refer the section "Receive Descriptor" [Page No:30–54] in ADSP-SC598 Hardware reference Manual from the below link,
www.analog.com/.../adsp-sc595-sc596-sc598-hrm.pdf

Can you clarify us on how you concluded that the HRM statement is not considered in the EMACPhyLoopback example code? If possible, could you share a screenshot with us.

Additionally, please confirm whether you are encountering any issues while running the loopback example.

Regards,
Nandini C