PCG CLK when working for SPORT TDM mode

Question

Hello, 
 My 21593 is using a 25MHZ crystal, and now I want to config my SPORT 0 working at TDM16 with 32bit, The clock should be 24.576MHz and FS should be 48KHz. However when I config the PCG I meet some problem, it seems the CLK can't be divide to 24.576MHz. and using "adi_sport_ConfigClock" function meet the same problem. What can I do to config my TDM clock? 
 Thanks

Ranji · Accepted Answer

Hi, Yes, your understanding is correct. Please let us know if you need any further assistance. Regards, Ranjitha R)

LinSiyu · Answer

Hi Ranji, 
 
 I see the documents and demo code and I use a SRU function connect the dai0_P15 to PCG clk in 
 
 SRU (DAI1_PB15_O,PCG0_EXTCLKA_I); ,and I config the PCG as : 
 
 void PCG_init ( void ) 
 { 
 ADI_PCG_CLK_INFO gClkInfoA = 
 { 
 ADI_PCG_CLK_EXT, /* Clock Source */ 
 1 u , /* Clock Divisor */ 
 false /* External Trigger */ 
 }; 
 
 ADI_PCG_FS_INFO gFsInfoA = 
 { 
 ADI_PCG_CLK_EXT, /* Clock Source */ 
 512 u , /* Frame Sync Divisor */ 
 256 u , /* Pulse Width */ 
 4 u , /* Phase */ 
 false , /* External Trigger */ 
 ADI_PCG_FSBYPASS_MODE_NORMAL /* Bypass Mode */ 
 }; 
 
 adi_pcg_Init (ADI_PCG_DEV_A, & gClkInfoA , & gFsInfoA ); 
 
 } 
 However when I measure the output of SPORT0A the clk is HIGH and framesync is LOW, is the way I use PCG error or some other reason? 
 
 Thanks, 
 Siyu

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PCG CLK when working for SPORT TDM mode