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ADSP-21593 Production
Reaching speeds of up to 1 GHz, the ADSP-2159x processors are members of the SHARC® family of products. The ADSP-2159x processor is a dual-SHARC+® core...
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ADSP-21593 on Analog.com

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In ADSP-21593, if I want to set sport0A as I2S RX, and the bit clk and fs clk are externally provided, do I need to config the sport clock and FrameSync?

    
		

			

									
					    WoA
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 16, 2024 
				
			
			
		
    
		
     
				
		
    
		    		    
		    
		    		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  ADSP-21593  
    
    		        		    		    	
			

    the bit clk and fs clk are externally provided, and there are 2 data inputs.
    

    this is my code:
    

    ```
    

    SRU(LOW, DAI0_PBEN07_I);
    SRU(LOW, DAI0_PBEN08_I);
    SRU(LOW, DAI0_PBEN03_I);
    SRU(LOW, DAI0_PBEN02_I);
    

    SRU(DAI0_PB07_O, SPT0_ACLK_I);
    SRU(DAI0_PB08_O, SPT0_AFS_I);
    SRU(DAI0_PB03_O, SPT0_AD0_I);
    SRU(DAI0_PB02_O, SPT0_AD1_I);
    

    adi_sport_Open(0, ADI_HALF_SPORT_A, ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, MemSPT_rx0, SPORT_MEMORY_SIZE, &hSPT_rx0);
    adi_sport_ConfigData(hSPT_rx0, ADI_SPORT_DTYPE_ZERO_FILL, 31, false, false, true);
    // adi_sport_ConfigClock(hSPT_rx0, 1, false, false, false); -> do i need to call this function?
    // adi_sport_ConfigFrameSync(hSPT_rx0, 64, false, false, false, false, true, true); -> do i need to call this function?
    adi_sport_DMATransfer(hSPT_rx0, spt_rx0_dma_list, BUF_NUM, ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM_SEC);
    adi_sport_CreateGlobalGroup(&hSPT_rx0, 1, &hSPT_group1_rx, false, true);
    adi_sport_GlobalRegisterCallback(hSPT_group1_rx, SPT_group1_rx_cb, &i2s_handle);
    adi_sport_GlobalEnable(true);
    ```
    

    

    in the example "GBL_Audio_Talk_I2S_21593_Core1", adi_sport_ConfigClock() and adi_sport_ConfigFrameSync() are not called. but it works fine.
    

    Under what circumstances should I call adi_sport_ConfigClock() and adi_sport_ConfigFrameSync() to config Clock and FrameSync?
    

    

    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Audio Signal Processors
                
                                                    
                 software
                
                                                    
                 SHARC Audio Processors/SoCs
                
                                                    
                 adsp-21593
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Apr 17, 2024 6:49 AM
            

            
					
      
	
      

		
		
      
					
      Hi,
      

      The adi_sport_ConfigClock() API is utilized to set up the clock for a specific SPORT device. It configures the SPORT device to utilize either an internal or external clock, selecting between rising or falling edges, and enabling gated Clock Mode.
      

      ADI_SPORT_RESULT adi_sport_ConfigClock(
                                              ADI_SPORT_HANDLE  hDevice,
                                              uint16_t          nClockRatio,
                                              bool              bUseIntlClock,
                                              bool              bFallingEdge,
                                              bool              bGatedClk
                                            )
      

      The parameter `bUseInternalClock` is a Boolean flag indicating whether to use the internal or external clock for data transmission. By default, device is configured to use the external clock. 
      

      If internal clock is chosen, the clock divider value needs to be set in the `nClockRatio` parameter.
      

      Similarly, the adi_sport_ConfigFrameSync() API is employed to set up the SPORT to use internal or external frame sync, specifying level or edge sensitivity, and early or late frame sync etc. 
      

      ADI_SPORT_RESULT adi_sport_ConfigFrameSync(
                                                   ADI_SPORT_HANDLE  hDevice,
                                                   uint16_t          nFsDivisor,
                                                   bool              bFSRequired,
                                                   bool              bInternalFS,
                                                   bool              bDataFS,
                                                   bool              bActiveHighFS,
                                                   bool              bLateFS,
                                                   bool              bEdgeSensitiveFS
                                                 )
      When `bInternalFS` parameter is set to true, it implies the use of internally generated frame sync. So, you need to configure the FS divider value based your requirement. However, if you're using an external clock and FS, there's no requirement to set the divider values.
      

      Please refer the below CCES help path to know about the descriptions of this API function parameters.
      CrossCore® Embedded Studio <version>> System Run-Time Documentation > System Services and Device Drivers > ADSP-SC594 Family (Cortex-A Core) API Reference > Modules >SPORT Device Driver
      

      Please refer the sections "Serial Clock" and "Frame Sync" to know about the formula for calculating the internal serial clock frequency and the frame sync frequency in the below link.
      https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2159x-sc591-592-594-hrm.pdf#page=2212
      

      These configurations can also be set via a static file.
      

      SSLDD 3.0 Device Drivers support the static configuration of the peripherals i.e. users can provide the required configuration parameters beforehand so that device driver can configure the peripheral in the initialization API. Static configuration header files contain set of configuration macros which device drivers use to configure the peripheral.
       
      adi_sport_config_SC59x.h is available in project > system > drivers> sport.
      

      In the GBL_Audio_Talk_I2S_21593_Core1 example is configured for external clock that is the SPORT device received their clock from DAC. These configurations are done in the static file mentioned above.
      

      Therefore, either you can use this API, or you can select the same in the static file (adi_sport_config_SC59x.h) file.
      

      Please let us know if you need any further assistance.
       
      Regards,
      Ranjitha R
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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