DDR3 sweep test failures when cycling temperature

Hi Greeny,

Please provide your comment on below points to assist you better on this issue.

1. Please confirm if you have adhered to the board design guidelines outlined in the Application note (EE-387).
https://www.analog.com/media/en/technical-documentation/application-notes/ee387v04.pdf#page=21
2. Could you please share your updated DMC_Registers_List.xlsx sheet? So that we can verify it as well.
3.Have you encountered any errors or exceptions during the process?
4. Please let us know whether you are aware of this below FAQ? If not, please compare the provided code with your application.
https://ez.analog.com/dsp/sharc-processors/adsp-sc5xxadsp-215xx/w/documents/15304/adsp-sc5xx-adsp-215xx---ddr-memory-test


Regards,
Ranjitha R

Hi Ranji,

Before answering your points, I'd like to provide updates and clarifications:

We are using is MT41K512M16VRP-107 AAT:P, which is a TwinDie part.

Regarding the periodic calibration, Micron's documentation states that a PRECHARGE command should be issued before a ZQCS command. We tried that and we had much better results than before, but we still get failures around 80C ambient temperature.

Now on your points:

1. Please confirm if you have adhered to the board design guidelines outlined in the Application note (EE-387).

To the best of my knowledge, yes. I’ll be in touch with our hardware engineers to verify this.

2. Could you please share your updated DMC_Registers_List.xlsx sheet? So that we can verify it as well.

/cfs-file/__key/communityserver-discussions-components-files/1009/DMC_5F00_Registers_5F00_List.xlsx

3. Have you encountered any errors or exceptions during the process?

No. The CPU itself is running happily. It is only the DDR memory test that is reporting errors.

4. Please let us know whether you are aware of this below FAQ? If not, please compare the provided code with your application.

The first difference I see is that in the code provided by the FAQ, the sweep test is in the SHARC+ core, while we run it in the ARM core. Is there any particular reason behind this choice?

I needed to disable the MDMA test sets as they were not working when ported to our project running on the ARM core. I’m assuming I am missing some startup configuration required for this but have not dug into it.

Cheers

Hi Greeny,

Sorry for the delay in getting back to you.

1. Could you please provide the precise part number of your processor?
2. If feasible, kindly inform us of the specific temperature range within which the failure occurs.
3. Based on your provided information, we have cross-referenced your configurations with the datasheet below. However, we were unable to locate data that matches your configurations exactly. If possible, could you please attach the datasheet for the DDR part so that we can double-check your configurations?
media-www.micron.com/.../ddr3l_8gb_x16_1cs_twindie_v00h.pdf
4. The ZQ calibration function is crucial for the proper operation of DDR3. Using an external resistor (240 Ω ± 1%) connected to the DMC_RZQ pin, DDR3 calibrates the Ron and Rtt values of the ZQ pin to accommodate temperature and voltage fluctuations. Similarly, on the processor end, there is an external resistor DMC_RZQ (34 Ω). It's important to note that a high-quality resistor of 34 Ohms with a 1% tolerance should be used at the processor end. This 34 Ohm resistor is utilized to configure our ODT. Kindly confirm whether it has been properly connected at both ends.

Regards,
Ranjitha.R

Hi Ranji,

Thanks for the reply.

Could you please provide the precise part number of your processor?

Processor part number is ADSP-SC572BBCZ-42

If feasible, kindly inform us of the specific temperature range within which the failure occurs.

Our main concern is we've seen a sweep test failure when the enclosure temperature was 37C. We have not been able to reproduce this failure. For tests without any ZQCS commands where the starting enclosure temperature is 20C and we raise the temperature to ~80C, the sweep test starts to fail at ~60C enclosure temp. With ZQCS the enclosure temperature can reach 80C before seeing failures. We do not have the TMU of the SHARC enabled, so we don't have temperatures from the SHARC itself. A nearby CPU reports temperatures between 70-75C when enclosure is 60C and 90C when enclosure is 80C.

We have similar results when the DSP is booted and DDR calibrated at enclosure temp of 80C - this is more stable even when temperature is lowered.

DDR data sheets

Yes that datasheet is what we started with, it references another data sheet. I'll attach both. There seems to be more failures with even byte addresses.

ZQ Calibration

We're running calibration from our init/preload code using code from EE-387 as a basis. SHARC documentation suggests ZQCL is part of startup and we see no difference in performance whether we run it explicitly or not - we believe ZQCL is issued by the DMC at initialization. Running ZQCS periodically has made a difference.

We want to integrate a hardware timer which runs ZQCS into our product. Should we be concerned about running ZQCS when our code is stored in DDR memory for both ARM and SHARC cores?

As an experiment, we lowered the CPU frequency of our ARM core to 400 MHz and used DDR800. Adjusting the timings. This produced our best result yet. Device had no failures in the sweep test after running for 2 hours at 87C enclosure temperature. I've attached the DMC configuration used for this test as welll.

/cfs-file/__key/communityserver-discussions-components-files/1009/DDR3L_5F00_8Gb_5F00_x16_5F00_1CS_5F00_TwinDie_5F00_V00H_2D00_1840279.pdf

/cfs-file/__key/communityserver-discussions-components-files/1009/4gb_5F00_automotive_5F00_ddr3l.pdf

/cfs-file/__key/communityserver-discussions-components-files/1009/DMC_5F00_Registers_5F00_List-DDR800.xlsx

Hi Greeny,

We understand that you are using MT41K512M16VRP-107 AAT:P DDR part. However, you are referring the base part number MT41K512M8 as per the suggestion given in the actual datasheet. Though, we couldn't locate the complete data for the DDR3-800 data rate variant from the datasheet. It appears that you've applied parameters relevant to the DDR part available in the EZ-kit (MT41K128M16-125) for latest variant.

Since you're using a different DDR part, specifically the MT41K512M16VRP-107 AAT:P, you should configure the values according to the 1866 data rate (for the -107-speed grade, the data rate is 1866 & for -25E/-25 speed grades, the data rate is 800). Please double-check and adjust the DDR registers based on your specific part number and share it with us.

Regarding "To the best of my knowledge, yes. I’ll be in touch with our hardware engineers to verify this."
>>>> Also please confirm with your hardware engineers once whether the board design guidelines have been followed as per applicable standards.

Regards,
Ranjitha R