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PORT Pull-up / Pull-down Register Clarification

Category: Datasheet/Specs
Product Number: ADSP-21593

Hi ADI Forum members, 

I'm after some clarification on the PORT (and DAI) pull-up / pull-down behaviour, as I'm seeing some contradictions between the hardware reference manual, datasheet and observed behaviour.

The datasheet states that PORT pins have "Programmable pull-up / pull-down", and the hardware reference manual states that there is PUE (pull-up Enable) and PDE (Pull-down Enable) registers. However the PDE register only contains a PUD (pull-up Disable) bit, which implies there is no pull-down and this register simply disables the pull-up. 

Not pulling a pin up is very different from pulling a pin down. The following truth table from the HRM also seems to imply that there is no pull-down, only disabling of the pull-up.



Contradictory to this, when observing a PORT pin and setting register values through the debugger I observe:

  • PUE = 0 && PDE = 0: line floats just above 0 (~36mV)
  • PUE = 1 && PDE = 0: line goes to 3.3V
  • PUE = 0 && PDE = 1: line goes to 0V

This is different behaviour to the table in the HRM. Is this an error in the HRM or am I misunderstanding something?

Adding further confusion is this statement regarding unused pins:
"For unused PORT/DAI pins, ensure that any unused pin does not go to floating state. Clear (=0) the
PUD bit of that pin."

This implies that clearing PDE prevents the line from floating, which is not what I observe and goes against my intuition of floating being not pulled in either direction (PDE and PUE cleared) and so to pull an unused pin low by setting PDE.

Could someone please clarify whether the 21593 does indeed have a pull-down or not, and provide some guidance on how to properly control pull-up / pull-down for pin inputs and also unused pins.

Many thanks in advance!



Added clarification on floating pin.
[edited by: cSmout1 at 10:31 AM (GMT -4) on 14 Mar 2024]
  • Hi,

    Thanks for posting your Query.

    We are checking on this case, will get back to you soon.

    Regards,

    Ranjitha.R

  • Hi Ranji,

    Nearly a month on, is there any response available to my query?

    Thanks, 

    Connor

  • Hi Connor,

    Sorry for the delay. We were discussing with design team to understand if this is correct and if what documentation part must be changed. In conclusion, PADS_PORT[n]_PDE ideally must have bits PDE (pull down enable) and NOT PUD (pull up disable). We will create an internal ticket to correct this. Thanks for pointing.

    Regards,

    Ranjitha.R

  • Hi Ranji, 

    Thanks for your response. Just to clarify, can I confirm that:

    - The documentation is incorrect, with the PDE Register needing PDE bits, not PUD
    - PORT pins have both a pull-up and pull-down that can be enabled?
    - That this logic is the same for DAI pins as it is for PORT pins.

    As for my later query, what should be done with unused PORT / DAI pins?

    Many thanks, 

    Connor

  • Hi Conor,
    Sorry for the late response.
    - The documentation is incorrect, with the PDE Register needing PDE bits, not PUD
    - PORT pins have both a pull-up and pull-down that can be enabled?
     
    >> Yes, your understanding is correct.
    - That this logic is the same for DAI pins as it is for PORT pins.
     
    >> Yes, applicable for DAI pins too.
    As for my later query, what should be done with unused PORT / DAI pins?
    >> HRM states "For unused PORT/DAI pins, ensure that any unused pin does not go to floating state. Clear (=0) the
    PUD bit of that pin
    >>> You can enable pull down for such pins.
    Regards,
    Ranjitha.R
  • Thank you for your response and clarification, we now understand this.

    Many thanks, 

    Connor