Hi Team,
I found the example code for SPI in the BSP. In that 21593 Core 1 using the DMA data transfer (SPI_DMA_MODE) but is it possible to use same in Core2?
Thanks,
Sushindren
ADSP-21593
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Reaching speeds of up to 1 GHz, the ADSP-2159x processors are members of the SHARC® family of products. The ADSP-2159x processor is a dual-SHARC+® core...
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ADSP-21593 on Analog.com
Hi Team,
I found the example code for SPI in the BSP. In that 21593 Core 1 using the DMA data transfer (SPI_DMA_MODE) but is it possible to use same in Core2?
Thanks,
Sushindren
Hi Sushindren,
Are you asking about the usage of same SPI peripheral in core 2. If so, it is not possible to use the same SPI peripheral in both cores simultaneously.
However, you can configure different SPI peripheral in both cores.
Regards,
Divya.P
Hi Divya,
Thank you for your support.
I am moving the SPI to core2 which is already present in Core1. Once moved to Core2, Core1 become Ideal (No SPI)
As you mentioned different SPI will work in both cores, I hope it will work in the above scenario also.
Thanks,
Divya P
Hi Sushindren,
You can use the code in Core2, there is no issue in it.
Please let us know if you face any problem while changing.
Regards,
Divya.P