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In ADSP21593 with CCES2.10.0, how to open DDR in 21593_preload_Core1 code.

Category: Software
Product Number: adsp-21593
Software Version: CCES2.10.0

For adsp-21593 debug, for core1 and core2 we need used DDR for 128M. For my understanding, the ldf config of 21593_preload_Core1 should follow our core1 real used ldf.

After I enable the LDF configuration external memory setting and rebuild 21593_preload_Core1, the loading preload always failed.

CCES version is 2.10.0.

ICE is ICE1000.

[TpsdkServer] Failed to load file: C:\Analog Devices\CrossCore Embedded Studio 2.10.0\SHARC\ldr\init_code\2159x_Init\21593_preload_Core1\Release\21593_preload_Core1.dxe [Error: Failed to connect to target., Code=0x80047344]

Follow is the system.svc of 21593_preload_Core1.

Follow is the system.svc of Core1.

If I disable the LDF configuration external memory in 21593_preload_Core1, it can load. But the DDR usage is not work as expected.

It seems the heap malloc in core1 during running time is not release after debug load.

Heap malloc always failed if I set malloc size as 0x1000000. If I small the malloc size to 0x700000, it can work with start address from 0x82000018.

It seems DDR 0x81000010 to 0x82000010 which malloced during run time in core1 before debug load is not released. 

Follow is the map of core1, the mem_DMC0_SDRAM_A6 is defined as SDRAM_STACK_HEAP_BLOCK.

During Core1 debug, the heap address after malloc is 0x82000018.