PHY is a physical layer interface of OSPI controller which is responsible for driving data/clocks and sampling data/clocks from the OSPI interface pins at high speed. By default PHY is not enabled in OSPI controller and all the transaction bypass the PHY and the operations are limited to 62.5 MHz. However when PHY is enabled, the OSPI can operate up to 125 MHz. In PHY mode controller can make use of an additional pin called DQS (Data strobe) which is driven by some flash devices which can operate at higher speeds. Since the DQS is driven by the flash along with the data of flash read operations, the skew between data and DQS is much smaller and predictable than between data from flash and clock from OSPI controller. This allows for reliable sampling of data at higher frequencies. With DQS enabled, OSPI in PHY mode can operate up to 125 MHz. However, if flash device does not support DQS, OSPI PHY can still operate with internal OSPI reference clock or loopback clock. In this case the frequency of operation is limited to 80 MHz. PHY also has a mechanism to adjust the sampling and driving of data through internal DLLs which can fine tune the timing delays for the data capture. These DLLs have to be configured to appropriate values for correct sampling which depends among other things on the flash device, board traces and operating conditions. Before doing any data accesses, it is expected to configure these delays to appropriate values which can be found through a PHY calibration training sequence which should be run upfront. ADI supplied device driver for OSPI provides an API to do this training and configure the PHY optimally before doing actual data accesses to flash device.
As explained in HRM, in PHY mode, OPSI interface clock (clock which goes to flash) is same as reference clock of OSPI. Since interface clock can not exceed 125 MHz, SYSCLK which is default clock to OSPI form CDU can not be always used as SYSCLK in the system may be much higher than 125 MHz . In such cases user has to make sure CDU is configure to select appropriate option form CDU to clock the OSPI reference clock which in within 125 MHz. Also the clock in PHY mode cannot be divided using BAUD setting in OSPI as this is ineffective in PHY mode and interface clock is always equal to reference clock
PHY is a physical layer interface of OSPI controller which is responsible for driving data/clocks and sampling data/clocks from the OSPI interface pins at high speed. By default PHY is not enabled in OSPI controller and all the transaction bypass the PHY and the operations are limited to 62.5 MHz. However when PHY is enabled, the OSPI can operate up to 125 MHz. In PHY mode controller can make use of an additional pin called DQS (Data strobe) which is driven by some flash devices which can operate at higher speeds. Since the DQS is driven by the flash along with the data of flash read operations, the skew between data and DQS is much smaller and predictable than between data from flash and clock from OSPI controller. This allows for reliable sampling of data at higher frequencies. With DQS enabled, OSPI in PHY mode can operate up to 125 MHz. However, if flash device does not support DQS, OSPI PHY can still operate with internal OSPI reference clock or loopback clock. In this case the frequency of operation is limited to 80 MHz. PHY also has a mechanism to adjust the sampling and driving of data through internal DLLs which can fine tune the timing delays for the data capture. These DLLs have to be configured to appropriate values for correct sampling which depends among other things on the flash device, board traces and operating conditions. Before doing any data accesses, it is expected to configure these delays to appropriate values which can be found through a PHY calibration training sequence which should be run upfront. ADI supplied device driver for OSPI provides an API to do this training and configure the PHY optimally before doing actual data accesses to flash device.
As explained in HRM, in PHY mode, OPSI interface clock (clock which goes to flash) is same as reference clock of OSPI. Since interface clock can not exceed 125 MHz, SYSCLK which is default clock to OSPI form CDU can not be always used as SYSCLK in the system may be much higher than 125 MHz . In such cases user has to make sure CDU is configure to select appropriate option form CDU to clock the OSPI reference clock which in within 125 MHz. Also the clock in PHY mode cannot be divided using BAUD setting in OSPI as this is ineffective in PHY mode and interface clock is always equal to reference clock
