For the ADSP-SC59x/ADSP-2159x set of processors, the following are the SWU instances and the memory regions that they monitor.
Memory address range
SWU name
SWU Memory region of monitoring
Start address (As mentioned in the data sheet)
End address (As mentioned in the data sheet)
SWU1
L2 Memory Core Port0 (CL2_0)
0x2000_0000
0x200F_FFFF
SWU2
L2 Memory DMA Port0 (DL2_0)
0x2000_0000
0x201F_FFFF
SWU3
L2 Memory Core Port1 (CL2_1)
0x2010_0000
0x201F_FFFF
SWU4
L2 Memory DMA Port1 (DL2_1)
0x2000_0000
0x201F_FFFF
SWU5
L2 Memory Core Port2 (CL2_2)
0x2000_0000
0x201F_FFFF
SWU7
SHARC0 Slave Port1
0x2824_0000
0x2839_FFFF
SWU8
SHARC0 Slave Port2
0x2824_0000
0x2839_FFFF
SWU9
SHARC1 Slave Port1
0x28A4_0000
0x28B9_FFFF
SWU10
SHARC1 Slave Port2
0x28A4_0000
0x28B9_FFFF
SWU11
System MMR (SMMR)
0x3000_0000
0x3FFF_FFFF
SWU12
SPI2/OSPI Flash Address space
0x6000_0000
0x7FFF_FFFF
SWU13
DMC0
0x8000_0000
0xBFFF_FFFF
Please note that there are three SWUs, SWU1 (CL2_0), SWU3 (CL2_1) and SWU5 (CL2_2) for L2 Memory Core access and two SWUs, SWU2 (DL2_0) and SWU4 (DL2_1) for L2 Memory DMA access. CL2_2, DL2_0 and DL2_1 have access to the entire L2 range. CL2_0 has access to the first 1MB and CL2_1 has access to the second 1MB of L2.
