Are all the TRU interrupts are level sensitive? If not, how can we re-configure it to edge sensitive?

No, only the TRU interrupts dedicated to SHARC cores, TRU Interrupts 4-11 are level sensitive. ARM core TRU interrupts, TRU Interrupts 0-3 are edge sensitive. To configure the ARM core interrupts to edge sensitive, the following code can be used

#include <services/int/adi_gic.h>

/* Configures the TRU Interrupt0 to edge sensitivity */
adi_gic_ConfigInt(INTR_TRU0_INT0,  ADI_GIC_INT_EDGE_SENSITIVE,  ADI_GIC_INT_HANDLING_MODEL_1_N);