How is memory mapped access to flash space controlled between SPI2 and OSPI ?
How is memory mapped access to flash space controlled between SPI2 and OSPI ?
Since both SPI2 and OSPI controllers can accesses the flash space(0x6000_0000 – 0x7FFF_FFFF(as mentioned in datasheet)) in memory mapped mode, there are control bits in REG_SCB5_REMAP register to control which controller is able to access this flash memory mapped space. Either OSPI or SPI2 can exclusively access whole of the flash memory space or there is an option to divide this space between OSPI and SPI2. Following are the three options for flash memory map configuration:
Last option(3) with REG_SCB5_REMAP = 0x2 is valid only for SC59x/2159x HPC package.
Since both SPI2 and OSPI controllers can accesses the flash space(0x6000_0000 – 0x7FFF_FFFF(as mentioned in datasheet)) in memory mapped mode, there are control bits in REG_SCB5_REMAP register to control which controller is able to access this flash memory mapped space. Either OSPI or SPI2 can exclusively access whole of the flash memory space or there is an option to divide this space between OSPI and SPI2. Following are the three options for flash memory map configuration:
Last option(3) with REG_SCB5_REMAP = 0x2 is valid only for SC59x/2159x HPC package.