ADSP-2156x TRU example code

This project demonstrates the Trigger Routing Unit(TRU) on ADSP-21569. UART is configured as TRU Slave and PINT1 is configured as TRU Master. After pressing the push button, the UART transfer is initiated. Refer the read_me.txt for more information. ADSP_21569_UART_SlaveTrigger.zip

ADSP-2156x Example code for MDMA

Attached is the MDMA bare-metal example code for ADSP-2156x. The L1 Private Memory space of SHARC+ can be accessed directly by itself without adding any offset. In order to access internal memories from peripheral DMA/Memory-to-memory DMA an offset (0x28000000) need to be added. In driver code, address conversion is taken care inside driver. MDMA_GUL.zip

What is Global SPORT Group Enable feature?

For some applications, enabling multiple SPORTs need to be synchronized so that all of them start and/or end at the same time. It may also be required to generate/receive a single interrupt/trigger for the DMA transfer of all the SPORTs in the same group. The DAI_GBL_SP_EN register is used to control enabling/disabling. The DAI_GBL_INT_EN register can be used to control interrupt/trigger generation/reception by multiple SPORTs in a group. In ADSP-2156x,each DAI has a DAI_GBL_SP_EN register. This register is used to enable the SPORTs globally. This works independent of SPORT enable in SPCTLx register. The enable feature in legacy SPORT remains same and can be used if the SPORTs has to be enabled individually. To enable the SPORTs grouped within the same DAI at the same time, write to the corresponding DAI_GBL_SP_EN register is required. If a group of SPORTs in different DAIs has to be enabled at the same time, write to the DAI_GBL_SP_EN.GBL_SP_EN field is required. This bit is reserved for the DAI1. Possible sport grouping for enabling globally, All 32 channels in 16 half SPORTs together. 16 channels in 8 half SPORTs in DAI0. 16 channels in 8 half SPORTs in DAI1. 8 channels in every 4 half SPORTs in each DAI. Within a DAI any number of groups are possible.

Graphical Demonstration of ADSP-2156x FIR/IIR Accelerator Performance and Real Time Usage

ADSP-2156x is the first 1 GHz single-core Digital Signal Processor in the SHARC®+ family of processors. ADSP-2156x incorporates high-performance FIR and IIR hardware accelerators. These accelerators can be run in tandem with the core to perform FIR and/or IIR processing, thereby increasing the overall processing capability of the processor. There are several functional and performance improvements on ADSP-2156x accelerators compared to its predecessors. This document provides a package of two GUIs to graphically demonstrate the performance of these accelerators and their usage in real time with different accelerator usage models. GUI1: ADSP-2156x FIR/IIR Accelerator Performance: This GUI can be used to visualize the expected performance of ADSP-2156x FIR/IIR accelerators for a given use case. This GUI generates the plots for ADSP-2156x FIR/IIR accelerator performance numbers for a given set of parameters such as block size, no. of taps/biquads, no. of channels, sample rate values, etc. Along with the ADSP-2156x accelerators, other target cases such as SHARC+ core only, ADSP-SC57x/SC58x/214xx accelerators and SHARC V (214xx) core are also covered for the sake of comparison. Different measurement unit options such as core cycles, time, MIPS, compute efficiency, and performance improvement factor are supported as well. The GUI uses data measured on the eval boards for different parameters and stored offline to generate the plots. GUI2: ADSP-2156x Accelerator Usage Models: This GUI demonstrates and compares different ADSP-2156x audio accelerator usage models in real time for different audio processing use cases. The real time use cases are run on the ADSP-21569 EZ-Kit. The GUI communicates with the EZ-Kit over UART to display the real-time information such as core and accelerator MIPS, core MIPS saving, and additional latency. The GUI can also be used to switch between the accelerator use cases and usage models dynamically. The software package can be downloaded from this link: ADSP-2156x Accelerator Performance GUI . The package also contains a user guide which can be used as reference while using these GUIs.

ADSP-2156x - DDR Sweep Test

Attached "DDR Sweep Test code" for ADSP-2156x which is performed for different types of accesses (e.g., core, DMA, 8-/16-/32-/64-bit) and different data patterns (for example, all 0x0, all 0xF, all 0x5, all 0xA, incremental, random, and all bits toggling). ADSP_21569_SweepTest.zip

Cache Examples for ADSP-2156X

Refer attached Examples for ADSP-2156X It contains the example codes for configuring L1 Instruction and Data Cache on ADSP-2156X. Example-1 : Locking of Data Cache By way. Example-2 : Cache write-back and write-through policy Example-3 : Configure Range registers and CCES cache support functions like flush_data_buffer. Example-4 : Address range based cache invalidation ADSPSC573 Example-5 : DM-PM Coherency in Cache. Example-6 : Maintaining data coherency between core and DMA by flushing cache before DMA. Example-7 : Maintaining data coherency between core and DMA by disabling cache. Refer to the readme.txt for more details on each project. Cache_Examples.zip

ADSP-2156x: FAQS - SPI Flash Read/Write using Device driver - Documents - ADSP-2156x

ADSP-2156x: FAQS - SPI Flash Read/Write using Device driver

This code is for SPI Flash Read/Write in ADSP-21569 Ez-Kit using Device driver. You can understand the working of the code from the comments embedded within.

Verify_flash_codes() will Verify Manufacturer ID and Device ID of Flash.

Erase_flash() will get number of sectors to erase the flash.

Write_flash() will choose between incremental data/ .Ldr data using #define INC according to the requirement and Write that data to flash.

Read_flash() will read the available data from flash.

SPI_Flash_GUL_Driver.zip