Q&A - Recent Threads

Relationship Between SCLK1 and the S/PDIF Receiver on ADSP-21562 at 192 kHz

Kasper Thomsen — Sat, 15 Aug 2026 02:39:47 GMT

Hi,

I'm working with an ADSP-21562 and using the internal S/PDIF receiver to receive audio. I'm trying to better understand the requirements for SCLK1 when operating at higher sample rates.

My questions are:

What is the exact relationship between SCLK1 and the incoming S/PDIF stream?
What are the requirements for the SCLK1 frequency to allow the S/PDIF receiver to reliably lock to and receive a 192 kHz audio stream?
Does SCLK1 need to meet a specific minimum frequency relative to the sample rate or recovered bit clock?
Is there a recommended safety margin above the minimum requirement?

I've reviewed the Hardware Reference Manual, but I'm still not clear on how the internal S/PDIF receiver depends on SCLK1 and how to determine the required SCLK1 frequency for stable operation at 192 kHz.

One additional observation from my testing is that I experience S/PDIF lock issues at 192 kHz when SCLK1 = 200 MHz, while operation stable when SCLK1 = 250 MHz. This suggests there may be a practical minimum SCLK1 requirement beyond what I have been able to identify in the documentation.

Has anyone encountered similar behavior or found any related guidance from Analog Devices?

Thanks in advance!

200R DDR3 memory clock termination

FlorianK — Wed, 05 Aug 2026 14:18:43 GMT

Hello,

we are currently working on a hardware design based on the ADSP-21569. The EV-21569-SOM evaluation board has been a great help in this regard.

One thing I don't fully understand is the 200 Ω differential termination resistor between DMC0_CK and DMC0_CK_N. My understanding is that the DMC interface provides on-die termination for the differential signals. If so, could you explain the purpose of the external termination resistor?

Best regards,
Florian

Thanks and best regards,

Florian

How to configure external clock for SPORT interface as described to get 62.5Mhz for receive

joelleoj — Wed, 08 Jul 2026 14:03:08 GMT

I plan to use adsp-2156x series of microcontrollers and i want to know what is meant my using SPORT with external clock and does using PCG count as an external clock in this case. As per the datasheet spec SPORT can receive data with external clock up to 62.5 MHz

Boot Mode to be used to program the external flash

tavinoth — Tue, 07 Jul 2026 13:33:41 GMT

I am using the EV-21569-SOM and an ICE-2000 emulator for programming.

My goal is to program the external flash using the emulator and then boot the DSP from the external flash.

Do we need to keep the DSP in No Boot/Custom Boot mode (BMODE[2:0] = 000) while programming the external flash using the ICE-2000 emulator, and then change BMODE to 001 for booting from the external flash?

Could you please confirm if this is the recommended procedure?

Schematic review.

LeverBridge — Fri, 05 Jun 2026 03:43:11 GMT

Hi everyone,

I'm hoping someone with experience across DSP, analog audio, and power design might be willing to cast an eye over my schematic. I'd be grateful for any feedback on errors, oversights, or improvements across all three sheets.

---

Page 1 — Analog Input & Codec

This page covers the input preamp stage through to the ADAU1761BCPZ codec. The preamp is built around an OPA134 op-amp with an MMBFJ113 JFET, feeding the ADAU1761 LINP pin single-ended, with LINN tied to CM. The CM pin has 10µF and 22µF in parallel to GND (32µF total). MONOOUT is used as the single output, via a 10µF capacitor and 100Ω series resistor to the output stage. The codec is configured via I²C and clocked via MCLK. ADDR0 and ADDR1 are both tied to GND giving address 0x38. IOVDD, AVDD, and DVDDOUT are all individually decoupled.

---

Page 2 — Power Section

Three rails generated from a 9V DC input:

- 3.3V: ADP7104ARDZ-3.3-R7 LDO. Input decoupled with 100nF, 4.7µF, and 10µF. Output decoupled with 100nF and 10µF.
- 1.1V: TPS62130A buck converter fed from 3.3V. Feedback resistor R24 (37.4kΩ) sets the output. L1 is 2.2µH. DEF pin tied to GND. FSW pin tied to GND (400kHz switching frequency). Output decoupled with 2.2µF and 22µF.
- 1.8V: AP2112K-1.8 LDO fed from 3.3V. EN tied to VIN. Input and output each decoupled with 1µF.

The clock is an ASV-24.576MHz active oscillator. EN tied to VDD (always enabled). Output fed via 22Ω to the DSP CLKIN net and via a separate 22Ω to the codec MCLK pin. Oscillator VDD decoupled with 100nF.

---

Page 3 — ADSP-21565 DSP Core

The DSP is the ADSP-21565BSWZ10 in 120-pin LQFP_EP package.

Power:
- VDD_INT (1.1V): 100nF per pin, bulk 10µF
- VDD_EXT (3.3V): 100nF per pin
- VDD_REF (1.8V): 10nF + 100nF per pin
- VDD_ANA (1.8V, Pin 85): 100nF + 10µF
- Exposed pad (Pin 121): GND

Boot mode: SYS_BMODE0 (Pin 105) pulled high via 10kΩ, SYS_BMODE1 (Pin 106) pulled low via 10kΩ — BMODE 01 = SPI boot.

Reset: SYS_HWRST (Pin 104) pulled high via 10kΩ with 100nF to GND.

Audio interface (DAI1, I²S): DAI1_PIN01/02/03/08 (Pins 77/76/75/70) connecting to ADAU1761 BCLK, LRCLK, ADC_SDATA, and DAC_SDATA respectively, each with 22Ω series resistors.

SPI flash: W25Q16JVSSQ connected on DAI1_PIN04–07 (Pins 74/73/72/71). WP and HOLD pulled high via 10kΩ to 3.3V.

I²C / TWI0: PA_10 (Pin 28) = SCL, PA_11 (Pin 34) = SDA. 2kΩ pull-ups to 3.3V on both lines.

JTAG: ICE-1000 compatible 14-pin header. TDI/TCK/TMS direct, TDO via 22Ω, TRST via 4.7kΩ pull-down to GND. VDDIO on header pulled up via 4.7kΩ to 3.3V. EMU left unconnected.

GPIO LEDs: Five LEDs on PA_00–PA_04 (Pins 14/15/16/18/19), each with a series current limiting resistor.

HADC pins (81–84): All tied directly to GND, unused.

---

My specific concerns are:
1. Power sequencing — does the ADSP-21565 have hard sequencing requirements between the 1.1V, 1.8V, and 3.3V rails, and does a passive approach satisfy them?
2. Are there any issues with the single-ended preamp into the ADAU1761 differential input as described above?
3. Any general errors or omissions I may have missed across any of the three pages.

I'm happy to share the schematic PDF with anyone willing to take a look. Thank you in advance.

Power rails

LeverBridge — Tue, 02 Jun 2026 15:58:49 GMT

"I'm designing a board around the ADSP-21565 with three power rails — 3.3V (ADP7104), 1.8V (AP2112K), and 1.1V (TPS62130A). The 1.8V feeds VDD_REF and VDD_ANA, the 1.1V feeds VDD_INT, and 3.3V feeds VDD_EXT. Does the ADSP-21565 have any hard power sequencing requirements between these rails, and if so, does a passive RC-based sequencing approach satisfy them or is active sequencing required?"

regards,

Mark.

DMC pin remap

David_Ashman — Mon, 11 May 2026 04:31:59 GMT

Hi -

I'm laying out a custom PCB with a 21569 and DDR3L memory. Using the ADSP-21569 SOM evaluation board layout as a guide, I see that the 16 bit data bus is bit-swapped in order to provide better routing paths and equidistant lengths. I'm struggling to find the registers used to provide lane/bit remapping to support this. Can anyone point me to that configuration section of code in the board support package?

Thanks in advance!

Dave

I want to extend the timer

mako2771 — Thu, 07 May 2026 10:23:50 GMT

Hi.

I am waiting for the filter to settle using a timer. While the timer was running, a change occurred in the filter. I want to reset the timer to allow time for the modified filter to settle.

How can I extend the duration of a timer while it is running?

What should I do?

I'm starting Timer like this.

*pREG_TIMER0_TMR1_WID=TIMER_WIDTH_10*WAITCOEF_GEQ[0];
*pREG_TIMER0_RUN=((1 << BITP_TIMER_RUN_TMR01) & BITM_TIMER_RUN_TMR01); // Enable the timer

Here are the timer settings

// Open the timer
adi_tmr_Open(GEQ_TIMER_NUM, TimerMemory01, ADI_TMR_MEMORY, TimerHandler_GEQ, NULL, &ghTimer01);
// Set the mode to PWM OUT
adi_tmr_SetMode(ghTimer01, ADI_TMR_MODE_SINGLE_PWMOUT);
// Set the timer width
adi_tmr_SetWidth(ghTimer01, TIMER_WIDTH_10);
// Set the timer_delay
adi_tmr_SetDelay(ghTimer01, TIMER_DELAY);
adi_tmr_EnableGracefulStop(ghTimer01, true);
adi_tmr_SetClkInSource(ghTimer01, ADI_TMR_CLKIN_SYSCLK);
adi_tmr_SetPulsePolarity(ghTimer01, false);
adi_tmr_DisableOutput(ghTimer01, true);
adi_tmr_SetEmuRun(ghTimer01, true);
adi_tmr_SetIRQMode(ghTimer01, ADI_TMR_IRQMODE_WIDTH_DELAY);
// Open the timer

Thanks & Best Regards,

YAMAMOTO

Secure SSL when Cache is enabled

BernhardM — Fri, 01 May 2026 06:27:32 GMT

Hi,

if using SecureBoot_OpenPart with cache enabled, adi_rom_Boot() failes.

If running without cache it succeeds.

Is there an example for a Secure Second Stage Loader with cache enabled?

Regards

Bernhard

ADSP-21565 ASRC Usage

pjs — Fri, 20 Mar 2026 07:06:50 GMT

I am currently using the ASRC module on the ADSP-21565. We require 12 input channels and 4 output channels, all in TDM8 format. There are two TDM input data lines: we need to capture all 8 channels from the first data line, and only the first 4 channels from the second data line. There is one TDM output data line, which uses only the first 4 channels. We plan to use 3 ASRC pairs for input processing and 1 ASRC pair for output. Is this achievable? If so, how should the ASRC be configured specifically?

How important is additional filtering on VDD_PLL and VDD_FPLLANA?

InoJosh — Wed, 04 Mar 2026 20:11:01 GMT

I have a design using the ADSP-21569.
I am potentially replacing it with ADSP-21834. I have already done so on a test board, and it is working.
But, there are power domains VDD_PLL and VDD_FPLLANA that don't get any special treatment on ADSP-21569 (they are just VDD_INT and VDD_REF).
Looking at the schematic for ADSP21835W-EV-SOM, there is additional filtering for both:

My design as it stands does not have this filtering, since it was designed with the ADSP-21569.
I know these are "pin compatible", but realistically, how important is this additional filtering? Do we need to do another board revision to add it in if switching to ADSP-21834?

Hardware Compatibility between ADSP-21569, ADSP-21593 and ADSP-21835

AlClark — Mon, 16 Feb 2026 18:08:08 GMT

We have board designs that support both ADSP-21569 and ADSP-21593. This means we have sufficient core supply for the 21593.

I understand that the ADSP-21835 is almost pin compatible. We boot from an external SPI flash and this has changed.

Can the ADI team outline the changes that are needed to do one or both of the following:

1. Changes needed to make an existing hardware design universal.
2. If this is impractical, then a complete list of changes needed.

I am sure many other users have this question and no one wants to do two revisions if they miss something the first time.

Al

System Crossbars (SCB)

daim — Thu, 05 Feb 2026 19:09:28 GMT

Hi.

I have some questions about System Crossbars (SCB).

1. Where is the Sharc+ core SCB on the Figure 41-3: SCB Block Diagram?

2. How can C0_I get access to L1 according Figure 41-5: SCB Block Diagram - Interconnections?

3. On 41–12 says

S2 slave port of SHARCs is intended primarily for MDMA between the L1 of the 2 SHARCs. Hence, only the Max BW MDMA is given access to S2 ports while all others masters are given access to S1 port.This arrangement also means that S1 and S2 port now share the same address space as against the ADSP-2156x family of processors where an alias address space was maintained.

Can you explain about the sentence which contains "the 2 SHARCs"?

Can you explain about the sentence which contains "as against the ADSP-2156x family"?

4. How do SCB Arbitration work in the case which describe below.

My case is a simple interaction between the internal core action and external devices. So my program do some work which are based on data from external devices and internal state machine variables.

At the same time:

4.1. MDMA channels copy L1-to-L1 memory : from Source_MDMA_Destination_CORE_DataBufL1 to Destination_MDMA_Source_CORE_DataBufL1.

4.2. The SHARC+ copy L1-to-L1 memory : from Destination_MDMA_Source_CORE_DataBufL1 to Source_MDMA_Destination_CORE_DataBufL1.

4.3. Source_MDMA_Destination_CORE_DataBufL1and Destination_MDMA_Source_CORE_DataBufL1 have the same memory bank.

Do SCB Arbitration work every 32 bit L1 memory transfer or every L1 memory transfer which has some package length?

Best regards,

Daim

EV-21569-SOM: Application Not Running After Reset When Loaded via JTAG

AD9364 — Fri, 23 Jan 2026 09:30:52 GMT

Hi,

I am working with the EV-21569-SOM board and loading my application using JTAG via CrossCore Embedded Studio (CCES).

I am able to successfully load the code through JTAG, but when the board is reset, the Power-On Self-Test (POST) code executes instead of my application.

I would like to understand how to prevent the POST from running and ensure that my application starts after reset when programming via JTAG only.
Please note that I am not using the serial port; all loading and debugging is performed exclusively through JTAG.

Any guidance on configuration settings, boot mode selection, or CCES options to achieve this would be helpful

DMA copy and copy working

daim — Fri, 09 Jan 2026 15:27:34 GMT

Hi.
Can you help me to understand my issue.
0. CCLK is 1GHz.
1. I have the code FUNC1 which execute some time T1 without any DMA and interrupts.
2. I have the code FUNC2
2.1. It config DMA to copy 4kBytes from L1 to L1 which may have same memory bank addresses
2.2. It start DMA and exit.
3. I compile with optimize_for_speed
4. My test program TST:
4.1. FUNC1.
4.2. FUNC2.
5. I see that FUNC2 in the program TST work some time T2.
6. And T2 is bigger than T1.
7. For example. T1 = 15us. T2 >= 16us.

I can explain it that DMA starts early and wins SCB arbitration. So the core waits when it can access to L1.

Is any idea?

Best regards.

DMC Initialization depending on anomaly 20000117

BernhardM — Wed, 07 Jan 2026 11:39:07 GMT

Hi,

what is the correct way to initailize the dmc depending on anomaly 20000117.

As i understand, the rom functions should not be used anymore.

Can you provide an example project.

Regards

Bernhard

external flash can be operated when JTAG has been locked

wuxiangzhi — Tue, 16 Dec 2025 09:12:30 GMT

Hello Support Team Guys,

We follow the link of "Emulation Key Disable - Q&A - ADSP-2156x - EngineerZone" for JTAG locking. Regarding the JTAG key protection of ADSP-21565, we hereby feedback our test and verification results, and have 2 questions that require your company’s response.

Regarding the issue of JTAG key protection for the ADSP21565, here is the feedback on the test verification results from our side:

According to the previous document "EmulationKeyDisable - Copy.zip," the current test results indicate that JTAG can be locked, and debugging via JTAG is indeed prevented.
However, even with JTAG locked, it is still possible to program the corresponding external Flash of the ADSP21565 via JTAG.
The method described in the "EmulationKeyDisable - Copy.zip" file for unlocking the JTAG interface by importing an XML file has not been successfully implemented by our team so far.

two questions:

We are currently puzzled because the JTAG key protection function for the ADSP21565 has not been successfully implemented. Is our approach incorrect, or does the ADSP21565 DSP chip itself not yet support this feature?
please clarify whether the ADSP21565 DSP can indeed implement JTAG key protection—specifically, whether JTAG can be locked to prevent programming the corresponding external Flash data via JTAG after locking, while still allowing unlocking via a key.

Thanks & Best regards,

xiangzhi wu

EMDMA and System MMR Latencies

daim — Sat, 06 Dec 2025 19:11:49 GMT

Hi.

Can you check me for EMDMA System MMR Latencies.

I took System MMR Latencies from ADSP-2156x SHARC+ Processor System Optimization Techniques (EE-412).

I use EMDMA TCBs for Standard Circular DMA. Each TCB copy one word from L1 memory to external (DDRIII) memory. I have 32 TCB list.

So EMDMA need to load 8 Registers for Standard Circular DMA . So it take 8*43=344 core cycles.

Than EMDMA must read data from L1 memory and write to external memory. I don't known how long it. I assume it be 43+44=87 core cycles.

Than EMDMA must renew External Index Register. It take 1*44=44 core cycles.

So one TCB need 344+87+44=475 core cycles.

32x TCB: 32*475=15200 core cycles.

Am I right?

Best regards.

CCES SRU configuration

Bajupi — Tue, 02 Dec 2025 05:04:50 GMT

I want to connect [ loudspeaker<-> EzKit <-> ADSP-21569-SOM <-> Brkout <-> AD2428WD1BZ <-> AD2428WC1BZ ] to make passthrough code.

In this connection, I set SRU init to connect [ ADSP-21569-SOM <-> Brkout <-> AD2428WD1BZ ].

This is my SRU init. Is there any error?

void SRU_Init(void)
{
/* Enable DAI pins */
*pREG_PADS0_DAI0_IE = 0x1ffffe;
*pREG_PADS0_DAI1_IE = 0x1ffffe;

/*==========================================================================
* A2B Interface (DAI0) - DSP is Master
* DAI0_PIN02: BCLK output to AD2428
* DAI0_PIN03: SYNC output to AD2428
* DAI0_PIN04: DTX0 input from AD2428
*========================================================================*/

/* PCG0 BCLK -> DAI0_PIN02 (output to A2B) */
SRU(PCG0_CLKA_O, DAI0_PB02_I);
SRU(HIGH, DAI0_PBEN02_I); /* Enable output */

/* PCG0 SYNC -> DAI0_PIN03 (output to A2B) */
SRU(PCG0_FSA_O, DAI0_PB03_I);
SRU(HIGH, DAI0_PBEN03_I); /* Enable output */

/* DAI0_PIN04 -> SPORT0A Data Input (A2B DTX0) */
SRU(DAI0_PB04_O, SPT0_AD0_I);
SRU(LOW, DAI0_PBEN04_I); /* Input */

/* PCG0 BCLK -> SPORT0A Clock */
SRU(PCG0_CLKA_O, SPT0_ACLK_I);

/* PCG0 SYNC -> SPORT0A Frame Sync */
SRU(PCG0_FSA_O, SPT0_AFS_I);

/*==========================================================================
* DAC Interface (DAI1) - DAC is Master (existing setup)
* DAI1_PIN05: BCLK from DAC
* DAI1_PIN04: FS from DAC
* DAI1_PIN01: Data to DAC
*========================================================================*/

/* DAC BCLK input */
SRU2(LOW, DAI1_PBEN05_I);

/* DAC BCLK -> SPORT4A and SPORT4B Clock */
SRU2(DAI1_PB05_O, SPT4_ACLK_I);
SRU2(DAI1_PB05_O, SPT4_BCLK_I);

/* DAC FS input */
SRU2(LOW, DAI1_PBEN04_I);

/* DAC FS -> SPORT4A and SPORT4B Frame Sync */
SRU2(DAI1_PB04_O, SPT4_AFS_I);
SRU2(DAI1_PB04_O, SPT4_BFS_I);

/* SPORT4A Data -> DAC */
SRU2(SPT4_AD0_O, DAI1_PB01_I);
SRU2(HIGH, DAI1_PBEN01_I); /* Enable output */

/* ADC Data -> SPORT4B (for RX) */
SRU2(DAI1_PB06_O, SPT4_BD0_I);
SRU2(LOW, DAI1_PBEN06_I); /* Input */

/* DAC BCLK -> ADC (for DAC clock reference) */
SRU2(DAI1_PB05_O, DAI1_PB12_I);
SRU2(HIGH, DAI1_PBEN12_I);

/* DAC FS -> ADC FS */
SRU2(DAI1_PB04_O, DAI1_PB20_I);
SRU2(HIGH, DAI1_PBEN20_I);
}

EMDMA and some questions

daim — Mon, 01 Dec 2025 12:28:15 GMT

Hi.

1. I can't find the information about EMDMA's word width. I find only that All the DMA addresses given by EMDMA are word-aligned byte addresses (p.28-3).

Am I right that EMDMA's word width is 32-bit?

2. HWR says that The EMDMA_CTL.WRBEN bit enables write back of the EIEP register after reads and or writes (p.28-24). But there are nothing about EIEP register.

I think It's from Legacy Sharc.

3. Functions as PrepareEmdmaTCBXY convert the address to system address space and shift right by 2 bits.

Do Shifting right by 2 bits because All the DMA addresses given by EMDMA are word-aligned byte addresses?

Enable BackChannel SigmaStudio+

EricSa — Thu, 27 Nov 2025 10:29:10 GMT

Hey together,

I'm getting forward with the evalutaion of the ADSP-21569. Now I'm at the point where i try to create my own project integrating SigmaStudio+ communication. So far everything goes well but I'm not able to enable the backchannel to SigmaStudio+. Here is my setup and what already works.

Setup: ADSP-21569-SOM + EV-SOMCRR-EZLITE

What already works:

- Audio from ADC to DAC via SPORT and DMA. ASRC runs, UART and TWI is running. I also can compile in SigmaStudio+ 2.4 with my DXE and download it to the ADSP-21569. The ADSP tells me that the SMAP is received and calls "adi_ss_schematic_process()" in a while loop everytime i receive a new packet from SPORT DMA.

What does not work:

- When the SMAP is downloaded, SigmaStudio+ tells "COMMUNICATION ERROR". I guess the "Perform target (DSP) verification after download" fails. But I can also see that there is no communication on the MISO pin. I dont know how to enable this communication.

For your reference here is my main code and the pinmux. But i can forward more details if required.

int main(int argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to 
	 * the project.
	 * @return zero on success 
	 */
	adi_initComponents();
	adi_pwr_SetClkOutSelectRegister(ADI_PWR_CGU0, ADI_PWR_CLKOUT_CGU0_SYSCLK0);
	/* Begin adding your custom code here */
	DEBUG_INFORMATION("Exploration SHARC\n");

    /* SigmaStudio+*/
#if SIGMA_STUDIO_ENABLE
    ADI_SS_MEM_BLOCK oConnectionMemBlk, *pConnectionMemBlk;
    ADI_SS_CONNECTION_CONFIG oConnConfig, *pConnConfig;
    ADI_SS_CONNECTION_RESULT eConnRet = ADI_SS_CONNECTION_FAILED;
    ADI_SS_CONNECTION_HANDLE hConnHandle;
    ADI_SS_MEM_BLOCK oCommMemBlk, *pCommMemBlk;
    ADI_SS_COMM_CONFIG oCommnConfig, *pCommnConfig;
    ADI_SS_COMM_RESULT eCommRet = ADI_SS_COMM_FAILED;
    ADI_SS_COMM_HANDLE hCommHandle;
    ADI_SS_RESULT eSSRes;
	SS_SMAP_SSN_INFO    *pSSnInfo;
	ADI_SS_COMM_PROPERTIES pCommProp;

    /* Connection component Initialization */
	pConnConfig = &oConnConfig;
	pConnConfig->eConnectionType = ADI_SS_CONNECTION_SPI;
	pConnConfig->nDevId = 1; //TODO: Modified from 1
	pConnConfig->eProcID = PROCESSOR_SH0;
	pConnectionMemBlk = &oConnectionMemBlk;
	pConnectionMemBlk->nSize = ADI_SS_CONNECTION_MEMSIZE;
	pConnectionMemBlk->pMem = adi_ss_connection_mem;
	eConnRet = adi_ss_connection_Init(pConnectionMemBlk, pConnConfig, &hConnHandle);
	if(eConnRet != ADI_SS_CONNECTION_SUCCESS){
		printf("\nConnection component initialization failed");
		return -1;
	}
	/* Communication component initialization*/
	pCommnConfig = &oCommnConfig;
	pCommnConfig->bCRCBypass = false;
	pCommnConfig->bFullPacketCRC = true;
	pCommnConfig->pfCommCmd4CallBack = (ADI_SS_COMM_CMD4_CB) adi_ss_comm_callback_cmd4;
	pCommnConfig->pfCommSMAPCallBack = (ADI_SS_COMM_SMAP_CB) adi_SMAP_Application_Callback;
	pCommnConfig->pfSPIRxIsrCallBack = (ADI_SS_COMM_APP_ISR_CB) adi_ss_spi_rx_callback;
	pCommnConfig->pfSPITxIsrCallBack = (ADI_SS_COMM_APP_ISR_CB) adi_ss_spi_tx_callback;
	pCommnConfig->hConnectionHandle = hConnHandle;
	pCommnConfig->pMemSMap[PROCESSOR_SH0] = &oSMAPSharc0;
	pCommnConfig->pBkChnlInfo[0] = &oBkChannelInfoSharc0;
	pCommMemBlk = &oCommMemBlk;
	pCommMemBlk->nSize = ADI_SS_COMM_MEMSIZE;
	pCommMemBlk->pMem = adi_ss_commn_mem;
	eCommRet = adi_ss_comm_Init(pCommMemBlk, pCommnConfig, &hCommHandle);
	if(eCommRet != ADI_SS_COMM_SUCCESS){
		printf("\nCommunication component initialization failed");
		return -1;
	}

//	eConnRet = adi_ss_connection_set_CommHandle(hConnHandle, hCommHandle);
//	if(eConnRet != ADI_SS_CONNECTION_SUCCESS){
//		printf("\nConnection component set comm failed");
//		return -1;
//	}

    /* Wait for SMAP to be received from host */
    while(!nSMAPReceived)
    {
    }
   /* Populating Memory addresses of different blocks from SMAP */
   oSSnMemMap.nMemBlocks = 11;
   pSSnInfo = &oSMAPSharc0.oSSnInfo[0];
   for(int i=0; i<oSSnMemMap.nMemBlocks; i++){
	   oSSnMemMap.pMemBlocks[i] = &pSSnInfo->oSSnBuff[i];
   }
   /* Create an instance of SSn */
   adi_ss_create( &hSSnHandle, &oSSnMemMap);
   if(hSSnHandle == NULL){
	   printf("\n SSn instance creation failed");
	   return -1;
   }
   /* Provide SSn handle to communication component using the adi_ss_comm_SetProperties() API */
   pCommProp.haSSnHandle[PROCESSOR_SH0][0] = hSSnHandle;
   pCommProp.nNumProcBlocks = 1;
   pCommProp.nProcId = PROCESSOR_SH0;
   eCommRet = adi_ss_comm_SetProperties(hCommHandle,ADI_COMM_PROP_SSN_HANDLE,&pCommProp);
   if(eCommRet != ADI_SS_COMM_SUCCESS){
     printf("\nError in Communication component");
     return -1;
   }
   /* Initialize the SSn instance */
   pSSnConfig = &oSSnConfig;
   pSSnConfig->hSSComm = hCommHandle;
   pSSnConfig->nBlockSize = BLOCK_SIZE ;
   pSSnConfig->nInChannels = 8;
   pSSnConfig->nOutChannels = 8;
   pSSnConfig->bSkipProcessOnCRCError = 0;
   pSSnConfig->bSkipInitialDownload = 0U;
   pSSnConfig->nInitNoWait = 0;
   pSSnConfig->eProcID = PROCESSOR_SH0;
   pSSnConfig->bClearUnusedOutput = 1;
   eSSRes =  adi_ss_init(hSSnHandle, pSSnConfig);
   if(eSSRes != ADI_SS_SUCCESS){
    printf("\nSSn instance initialization failed");
    return -1;
   }
   pSSnProperties = &oSSnProperties;
   /* Initialize SigmaStudio I/O pointers */
   for(int i=0; i<NUM_CHANNELS; i++){
    pSSInBuff[i] = &aSSInOutBuff[i*BLOCK_SIZE];
    pSSOutBuff[i] = pSSInBuff[i];
   }

   eCommRet = adi_ss_comm_GetProperties(hCommHandle, &pCommProp);
   if(eCommRet != ADI_SS_COMM_SUCCESS){
	   printf("\nError in Communication get properties");
	   return -1;
   }

//	eConnRet =  adi_ss_connection_Enable(hConnHandle);
//	if(eConnRet != ADI_SS_CONNECTION_SUCCESS){
//		printf("\nConnection component enable failed");
//		return -1;
//	}
	#endif

	#if ADSP_I2S_MASTER
	DEBUG_INFORMATION("SHARC runs as clock master\n");
	#else
	DEBUG_INFORMATION("SHARC runs as clock slave\n");
	#endif
	ADI_UART_RESULT    eUartResult;
	ADI_TWI_RESULT 	eTwiResult;
    /* Open UART */
	eUartResult = adi_uart_Open(ADI_UART_0, ADI_UART_DIR_BIDIRECTION, Uart0Memory, ADI_UART_BIDIR_MEMORY_SIZE, &hDev0);
    CheckResult(eUartResult);
    eUartResult = adi_uart_ConfigBaudRate(hDev0, 1, 2170u); /* Prescaler: 1, Divisor: 2170 = 57600 Baudrate */
    CheckResult(eUartResult);
    char testBuffer[100] = "Hello from Eric Blocking \n";
    eUartResult = adi_uart_CoreWrite(hDev0, testBuffer, strlen(testBuffer));
    /* Open TWI */
    int result = SPU_init();
//    int result = SUCCESS;
    if(result == SUCCESS){
    	result = ADAU1372_init(!slave);
    	if(result == SUCCESS){
    		result = Sport_init(slave);
    		if(result == SUCCESS){
    			Stop_TWI();
    		}
    	}
    }
    /* Copy Dummy values for SS */
    for(uint32_t ch = 0; ch < NUM_CHANNELS; ++ch){
    	for(uint32_t sample = 0; sample < BLOCK_SIZE; ++sample){
    		nTempBuff[ch*BLOCK_SIZE + sample] = ch;
    	}
    }

	/* Populating hardcoded values for readback */
	for(int i=0; i<2; i++)
	{
		oBkChannelInfoSharc0.nAvgMIPS[i]=10.0;
		oBkChannelInfoSharc0.nPeakMIPS[i]=20.0;
		oBkChannelInfoSharc0.nVersionInfo=0x47000000;
	}

	DEBUG_INFORMATION("Process SigmaStudio\n");

    while(1){
    	Sport_loop();
		while(!Sport_isDataReceived());
		Sport_clearDataReceived();
		/* Fixed to float conversion and copy to SS input buffer */
		for(uint32_t ch = 0; ch < NUM_CHANNELS; ch++){
			//CopyFix2Float((volatile uint32_t*)&pSportIn[i], NUM_CHANNELS, pSSInBuff[i], 1, BLOCK_SIZE, 1u);
			CopyFix2Float((volatile uint32_t*)&nTempBuff[ch], NUM_CHANNELS, pSSInBuff[ch], 1, BLOCK_SIZE, 1u);
		}
		DEBUG_INFORMATION("call adi_ss_schematic_process\n");
		adi_ss_schematic_process(hSSnHandle,BLOCK_SIZE,(adi_ss_sample_t **)pSSInBuff,(adi_ss_sample_t **)pSSOutBuff,pSSnProperties);

	}
//	return 0;
}

By the way: The function "adi_ss_schematic_process()" is really called. I added a print out before. Here you can see the output of the debug log.

Exploration SHARC
SigmaStudio+ SMAP received
SHARC runs as clock master
GPIO: PB03 Vol Up, PB05 Vol Down
PCG: Use Precision Clock Generator for SPORTs
SPORT: ASRC DAI1 send to DAC
SPORT: Only 2 channels are received
Process SigmaStudio
Process SigmaStudio
ASRC Device Initialized Callback Received, Ratio: 0.93, SR 51.60 kHz
call adi_ss_schematic_process
call adi_ss_schematic_process
call adi_ss_schematic_process
call adi_ss_schematic_process

Thanks a lot for your help in advance.

Best regards,

Eric

ASRC 16 Bit left justified to I2S

EricSa — Wed, 29 Oct 2025 15:16:57 GMT

Hey together,

I have another question regarding the SPORTs and the ASRC of the ADSP-21569. Maybe you can help. So far I am able to receive and transmit data via SPORT + DMA while running the ADSP als clock master. I also tried it by using the internal clock for the SPORTs as well as the PCGA as clock source. Everything fine so far. Now I am trying to get the ASRCs running. Here I'm a bit lost and I get only some crappy noise out of the DAC.

My plan is the following:

The first question would be:

- Q1: Is it really required to route the CRS outputs of the PCGA to a DAI1 PinBuffer? Is there no internal way to route the signals from PCGA to DAI1?

- Q2: How should the configuration of the ASRC look like? What is right in my setup and what is wrong?

- Q3: When I am using the PCGA as clock source for the SPORTs, is the "nClockRatio" in the adi_sport_ConfigClock() required?

Below is my code for the ASRC and the SPORT4A. Excuse by rought code, it is really hardcoded stuff but it is just for evaluation purpose.

#define COUNT 128
ADI_CACHE_ALIGN static int   int_SP4ABuffer0[COUNT];
ADI_CACHE_ALIGN static int   int_SP4ABuffer1[COUNT];

ADI_PDMA_DESC_LIST iSRC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP4A;
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static ADI_SPORT_HANDLE hSPORTDev4ARx; //ASRC RX

/*
Static Code for all other SPORTs and DMAs ...
*/


int SPU_init(void){
    if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to initialize SPU service\n");
		return FAILED;
    }

    /* Make SPORT 3A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_3A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT3A\n");
		return FAILED;
    }

    /* Make SPORT 3B to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_3B_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT3B\n");
		return FAILED;
    }

    /* Make SPORT 4A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_4A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT4A\n");
		return FAILED;
    }

    return SUCCESS;
}

static void PCG_init(void){
	ADI_PCG_CLK_INFO gClkInfoA;
	gClkInfoA.eClkInput = ADI_PCG_CLK_SCLK0;               /* Clock Source */
	gClkInfoA.nDiv = OUTPUT_PCG_CLOCK_DIV;               /* Clock Divisor */
	gClkInfoA.bExternalTrigger = false;                    /* External Trigger */

	ADI_PCG_FS_INFO gFsInfoA;
	gFsInfoA.eClkInput = ADI_PCG_FS_SCLK0;                 					/* Clock Source */
	gFsInfoA.nDiv = (OUTPUT_PCG_CLOCK_DIV)*(ADI_SPORT0A_CTL_SLEN + 1)*(2);	/* Frame Sync Divisor */
	gFsInfoA.nPulseWidth = (gFsInfoA.nDiv)/2;              					/* Pulse Width */
	gFsInfoA.nPhase = (OUTPUT_PCG_CLOCK_DIV)/2;                  			/* Phase */
	gFsInfoA.bExternalTrigger = false;                     					/* External Trigger */
	gFsInfoA.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL; 					/* Bypass Mode */

	adi_pcg_Init(ADI_PCG_DEV_A,&gClkInfoA,&gFsInfoA);

}

static int ASRC_init(void){
	ADI_ASRC_RESULT eAsrcResult = ADI_ASRC_FAILED;
	eAsrcResult = adi_asrc_Open(1u,                   /* Block number */
								0u,                   /* Device number */
								gAsrcMem,             /* Pointer to Memory */
								ADI_ASRC_MEMORY_SIZE, /* Memory Size */
								&hAsrc);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Open ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}
	eAsrcResult = adi_asrc_SetSerialFormat(hAsrc, ADI_ASRC_INPUT_16BIT_RIGHT_JUSTIFIED, ADI_ASRC_OUTPUT_I2S, ADI_ASRC_WORD_LENGTH_24);

    eAsrcResult = adi_asrc_RegisterCallback(hAsrc,AsrcCallback,NULL);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Register callback for ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}

	eAsrcResult = adi_asrc_Enable(hAsrc,true);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Enable ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}

	return SUCCESS;
}

static void PrepareDescriptors (void)
{

	iDESC_LIST_1_SP3A.pStartAddr	= (int *)int_SP0ABuffer1; /* Data array */
	iDESC_LIST_1_SP3A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP3A.XCount		= COUNT;
	iDESC_LIST_1_SP3A.XModify		= 4; /* Increase data address */
	iDESC_LIST_1_SP3A.YCount		= 0;
	iDESC_LIST_1_SP3A.YModify		= 0;
	iDESC_LIST_1_SP3A.pNxtDscp		= &iDESC_LIST_2_SP3A;

	iDESC_LIST_2_SP3A.pStartAddr	= (int *)int_SP0ABuffer2; /* Data array */
	iDESC_LIST_2_SP3A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP3A.XCount		= COUNT;
	iDESC_LIST_2_SP3A.XModify		= 4; /* Increase data address */
	iDESC_LIST_2_SP3A.YCount		= 0;
	iDESC_LIST_2_SP3A.YModify		= 0;
	iDESC_LIST_2_SP3A.pNxtDscp		= &iDESC_LIST_1_SP3A; /* Points to the first descriptor */

	iSRC_LIST_1_SP4A.pStartAddr	= (int *)int_SP4ABuffer0; /* Data array */
	iSRC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_1_SP4A.XCount		= COUNT;
	iSRC_LIST_1_SP4A.XModify		= 4; /* Increase data address */
	iSRC_LIST_1_SP4A.YCount		= 0;
	iSRC_LIST_1_SP4A.YModify		= 0;
	iSRC_LIST_1_SP4A.pNxtDscp		= &iSRC_LIST_2_SP4A;

	iSRC_LIST_2_SP4A.pStartAddr	= (int *)int_SP4ABuffer1; /* Data array */
	iSRC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_2_SP4A.XCount		= COUNT;
	iSRC_LIST_2_SP4A.XModify		= 4; /* Increase data address */
	iSRC_LIST_2_SP4A.YCount		= 0;
	iSRC_LIST_2_SP4A.YModify		= 0;
	iSRC_LIST_2_SP4A.pNxtDscp		= &iSRC_LIST_1_SP4A; /* Points to the first descriptor */
}

static void SPORTCallback(void *pAppHandle,uint32_t nEvent,void *pArg){
	int i;
    /* CASEOF (event type) */
    switch (nEvent){
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        	adi_gpio_Toggle(GPIO_DAC_PORT,GPIO_DAC_PIN);
        break;
        default:
        break;
    }
}


static void SPORTCallbackASRC(void *pAppHandle, uint32_t nEvent, void *pArg){
	int i;
    /* CASEOF (event type) */
    switch (nEvent){
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        	adi_gpio_Toggle(GPIO_ASRC_PORT,GPIO_ASRC_PIN);
			#if FORWARD_ASRC
			TestCallbackCount +=1;
			AsrcCallbackCount +=1;
			if(AsrcCallbackCount==1){
				for(i=0;i<COUNT;i+=2){
					int_SP0ABuffer1[i]=int_SP4ABuffer0[i];/*Copy ASRC Buffer to DAC */
					int_SP0ABuffer1[i+1]=int_SP4ABuffer0[i+1];/*Copy ASRC Buffer to DAC */
					++copyCount;
				}
			}
			if(AsrcCallbackCount==2){
				for(i=0;i<COUNT;i+=2){
					int_SP0ABuffer2[i]=int_SP4ABuffer1[i];/*Copy ASRC Buffer to DAC */
					int_SP0ABuffer2[i+1]=int_SP4ABuffer1[i+1];/*Copy ASRC Buffer to DAC */
					++copyCount;
				}
				AsrcCallbackCount=0;
			}
			#endif
        break;
        default:
        break;
    }
}

int Sport_init(bool slave, bool rxCH12, bool rxCH34){

	PCG_init();

    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 3a */
	eResult = adi_sport_Open(SPORT_DEVICE_3A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_I2S_MODE, SPORTMemory3A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev3ATx);
	/* Try to enable the clock */
	adi_sport_ConfigClock(hSPORTDev3ATx,39,false,false,false);
	adi_sport_ConfigFrameSync(hSPORTDev3ATx,ADI_SPORT0A_CTL_SLEN,false,false,false,true,false,false);


	/* Open the SPORT Device 3B*/
	eResult = adi_sport_Open(SPORT_DEVICE_3B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory3B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev3BRx);
	adi_sport_ConfigClock(hSPORTDev3BRx,39,false,false,false);
	adi_sport_ConfigFrameSync(hSPORTDev3BRx,ADI_SPORT0A_CTL_SLEN,false,false,false,true,false,false);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev3BRx,SPORTCallback,NULL);
	eResult = adi_sport_RegisterCallback(hSPORTDev3ATx,SPORTCallbackTx,NULL);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Open the SPORT Device 4A ASRC */
	eResult = adi_sport_Open(SPORT_DEVICE_4A, ADI_HALF_SPORT_A, ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory4A, ADI_SPORT_MEMORY_SIZE, &hSPORTDev4ARx);
	CHECK_RESULT(eResult);
	adi_sport_ConfigData(hSPORTDev4ARx, ADI_SPORT_DTYPE_SIGN_FILL, 31, false, true, false);
	adi_sport_ConfigClock(hSPORTDev4ARx, 39, false, false, false);
	adi_sport_ConfigFrameSync(hSPORTDev4ARx, 31, false, false, false, false, false, false);
	eResult = adi_sport_RegisterCallback(hSPORTDev4ARx, SPORTCallbackASRC, NULL);
	ASRC_init();
	eResult = adi_sport_DMATransfer(hSPORTDev4ARx,&iSRC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev3BRx,&iSRC_LIST_1_SP3B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	eResult = adi_sport_DMATransfer(hSPORTDev3BRx,&iSRC_LIST_1_SP3B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_SEC);

	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev3ATx,&iDESC_LIST_1_SP3A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);

	/*Enable the Sport Device 4B */
	eResult = adi_sport_Enable(hSPORTDev3BRx,true);
	/*Enable the Sport Device 3a */
	eResult = adi_sport_Enable(hSPORTDev3ATx,true);
	/*Enable the Sport Device 4a */
	eResult = adi_sport_Enable(hSPORTDev4ARx,true);
	return eResult;
}

int main(int argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to 
	 * the project.
	 * @return zero on success 
	 */
	adi_initComponents();
	adi_pwr_SetClkOutSelectRegister(ADI_PWR_CGU0, ADI_PWR_CLKOUT_CGU0_CCLK0);
	/* Begin adding your custom code here */
	ADI_UART_RESULT    eUartResult;
	ADI_TWI_RESULT 	eTwiResult;
    if(result == SUCCESS){
    	result = ADAU1372_init(!slave);
    	if(result == SUCCESS){
    		result = Sport_init(slave, rxCH12, rxCH34);
    		if(result == SUCCESS){
    		
    		}
    	}
    }
    while(1){

	}
//	return 0;
}

Thanks a lot in advance.

Best regards,

Eric

UART - DMA Descriptor Mode Ping Pong Buffer

SagiS — Mon, 20 Oct 2025 14:49:47 GMT

Hi,

I work with the ADSP21565 and I want to implement a UART communication based on DMA with descriptor list mode with ping pong buffering (2 buffers for RX and 2 for TX).

I can't find any example for it, all I can find is an example with a single buffer.

Is there any example? as I don't think changing the DMA_NUM_DESC macro to 2 is enough.

Thanks,

Sagi.

Selection of DAI0/1 pins when there's limited pin count

Hfuhruhurr — Sun, 21 Sep 2025 13:45:34 GMT

Hi all,

say, we have a board which we want to equip with an ADSP21569 but we have limited pin count and can connect only 20 DAI pins.

Thus, we have to leave some DAI0/1 pins unconnected.

As I understand, the DAI0/1 pins 3/4/5/6 have an additional value as they can be cross connected to the other DAI.

Pins 19/20 have additional value as they can change the signal polarity in hardware.

I'd leave DAI pins 7/8/9/10 unconnected, then.

Is there any downside when doing so?

Are there any limitations when using DAI0/1 pins 3/4/5/6 ?

Best regards,

Rainer

extended precision (40 bit) float

daim — Fri, 22 Aug 2025 09:35:12 GMT

Hi.

I Where can I find IIR Filter Response example which is mentioned in

The thread Convert from 64bit floating point data to 40bit floating point data is about how convert 40 bit float to double and vice versa. It prepare for hardware unit of Sharc++ processor.

But I can't use it for core calculation with extended precision (40 bit) float.

For Legacy Sharc I can use 48 bit width memory and do ALU/multiplier core operations which used extended precision (40 bit) float.

For Sharc++ I can't solution how use ALU/multiplier core operations which used extended precision (40 bit) float if the char size is 8 bits.

I think I need the code in C/C++ as the code which used in CCES_HOME\SHARC\lib\src\osal_noos\Ports\SHARC\CCES\adi_osal_noos_arch_a.asm

Something like that for load 40 bit float from long long
px = dm(-24, i6) (lw); r0 = px;

Something like that for save 40 bit float to long long
px = r0; dm(-24, i6) = px (lw);

But I can't understand how it desire with asm() construct.

Best regards.