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ADSP-21569 Recommended for New Designs
Reaching speeds of up to 1 GHz, the ADSP-2156x processors are members of the SHARCÂ® family of products. The ADSP-2156x processor is based on the SHARC...
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ADSP-21569 on Analog.com

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200R DDR3 memory clock termination

FlorianK on Aug 5, 2026

Category: Hardware

Product Number: EV-21569-SOM

Hello,

we are currently working on a hardware design based on the ADSP-21569. The EV-21569-SOM evaluation board has been a great help in this regard.

One thing I don't fully understand is the 200 Ω differential termination resistor between DMC0_CK and DMC0_CK_N. My understanding is that the DMC interface provides on-die termination for the differential signals. If so, could you explain the purpose of the external termination resistor?

Best regards,
Florian

Thanks and best regards,

Florian

Ranji

on Aug 6, 2026 10:42 AM
0
Hi,

The 200 Ω differential termination resistor between DMC0_CK and DMC0_CK_N is used to properly terminate the DMC differential clock signal and improve signal integrity.

All the DDR interface signals without ODT require external termination for improved signal integrity.

As per the EE-418 application note, The DMC_CK and /DMC_CK signals must be terminated using a differential termination scheme.

Please refer the below linked application note EE-418 “ADSP-2156x Board Design Guidelines for Dynamic Memory Controller” which provides recommended board design practices for interfacing DDR memory and achieving expected performance from the controller.
https://www.analog.com/media/en/technical-documentation/application-notes/ee418v02.pdf

Regards,
Ranjitha R
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FlorianK on Aug 10, 2026 7:51 AM in reply to Ranji
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Hi Ranjitha,

thanks for your answer. I read through the application note again more carefully, and it makes sense now.

Best regards,

Florian
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200R DDR3 memory clock termination

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