ADSP-21560
Recommended for New Designs
Reaching speeds of up to 1 GHz, the ADSP-21560/ADSP-21561/ADSP-21564 processors are members of the SHARC® family of products. These processors offer a...
Datasheet
ADSP-21560 on Analog.com
I plan to use adsp-2156x series of microcontrollers and i want to know what is meant my using SPORT with external clock and does using PCG count as an external clock in this case. As per the datasheet spec SPORT can receive data with external clock up to 62.5 MHz
NandiniC - Moved from Precision Microcontrollers to ADSP-2156x. Post date updated from Monday, June 15, 2026 9:26 AM UTC to Wednesday, July 8, 2026 2:03 PM UTC to reflect the move.
Hi,
When the SPORT is configured for external clocking, the clock rate is determined by the external source providing the clock to the SPORT clock pin. You can configure and generate the required clock using the PCG via DAI pins.
As mentioned in the datasheet, the SPORT supports receiving data with an external clock frequency of up to 62.5MHz.
We would suggest you to refer the SPORT examples available in the ADSP-2156x Board support package. The BSP can be downloaded from the following link.
download.analog.com/.../ADI_EV-2156x_EZ-KIT-Rel3.0.0.exe
Once installed, you can find the example from the below mentioned path.
[Installation directory]:\Analog Devices\EV-2156x_EZ-KIT-Rel3.0.0\EV-2156x_EZ-KIT\Examples\drivers\sport
Regards,
Nandini C
Hi,
Thank you for your reply and clarifying my doubt.
I had an other doubt regarding the capability of the PCG. Suppose i have a sensor for which i need to give the clock and frame sync and in return it sends the data.
So in this case i would like to know the max clock the PCG can generate so that i can give it to both my sensor and my controller board. Would it be able to support generating clocks upto 62.5 MHz?
Hi,
The PCG can generate a pair of signals (clock and frame sync) derived from a clock input signal (SCLK0, SYS_CLKIN0, or DAI pin buffer). The maximum clock that the PCG can generate depends on the selected clock source.
For example, if the PCG clock source is SCLK0=125MHz and CLKDIV = 2, then the generated bit clock(BCLK) will be 62.5MHz.
Please ensure that the sensor you are using supports a 62.5MHz clock.
Regards,
Nandini C
Hi,
Thank you for clearing my doubt.
Regards,
Joel