| SLA Status | Assignee | Support Status |
|---|---|---|
| SLA Closed. Met after 7 hours |
DaveThib |
Awaiting Customer Response |
ADAU1761
Production
The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 14 mW from...
Datasheet
ADAU1761 on Analog.com
ADSP-21565
Recommended for New Designs
Reaching speeds of up to 1 GHz, the ADSP-2156x processors are members of the SHARC® family of products. The ADSP-2156x processor is based on the SHARC...
Datasheet
ADSP-21565 on Analog.com
Hi everyone,
I'm hoping someone with experience across DSP, analog audio, and power design might be willing to cast an eye over my schematic. I'd be grateful for any feedback on errors, oversights, or improvements across all three sheets.
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Page 1 — Analog Input & Codec
This page covers the input preamp stage through to the ADAU1761BCPZ codec. The preamp is built around an OPA134 op-amp with an MMBFJ113 JFET, feeding the ADAU1761 LINP pin single-ended, with LINN tied to CM. The CM pin has 10µF and 22µF in parallel to GND (32µF total). MONOOUT is used as the single output, via a 10µF capacitor and 100Ω series resistor to the output stage. The codec is configured via I²C and clocked via MCLK. ADDR0 and ADDR1 are both tied to GND giving address 0x38. IOVDD, AVDD, and DVDDOUT are all individually decoupled.
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Page 2 — Power Section
Three rails generated from a 9V DC input:
- 3.3V: ADP7104ARDZ-3.3-R7 LDO. Input decoupled with 100nF, 4.7µF, and 10µF. Output decoupled with 100nF and 10µF.
- 1.1V: TPS62130A buck converter fed from 3.3V. Feedback resistor R24 (37.4kΩ) sets the output. L1 is 2.2µH. DEF pin tied to GND. FSW pin tied to GND (400kHz switching frequency). Output decoupled with 2.2µF and 22µF.
- 1.8V: AP2112K-1.8 LDO fed from 3.3V. EN tied to VIN. Input and output each decoupled with 1µF.
The clock is an ASV-24.576MHz active oscillator. EN tied to VDD (always enabled). Output fed via 22Ω to the DSP CLKIN net and via a separate 22Ω to the codec MCLK pin. Oscillator VDD decoupled with 100nF.
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Page 3 — ADSP-21565 DSP Core
The DSP is the ADSP-21565BSWZ10 in 120-pin LQFP_EP package.
Power:
- VDD_INT (1.1V): 100nF per pin, bulk 10µF
- VDD_EXT (3.3V): 100nF per pin
- VDD_REF (1.8V): 10nF + 100nF per pin
- VDD_ANA (1.8V, Pin 85): 100nF + 10µF
- Exposed pad (Pin 121): GND
Boot mode: SYS_BMODE0 (Pin 105) pulled high via 10kΩ, SYS_BMODE1 (Pin 106) pulled low via 10kΩ — BMODE 01 = SPI boot.
Reset: SYS_HWRST (Pin 104) pulled high via 10kΩ with 100nF to GND.
Audio interface (DAI1, I²S): DAI1_PIN01/02/03/08 (Pins 77/76/75/70) connecting to ADAU1761 BCLK, LRCLK, ADC_SDATA, and DAC_SDATA respectively, each with 22Ω series resistors.
SPI flash: W25Q16JVSSQ connected on DAI1_PIN04–07 (Pins 74/73/72/71). WP and HOLD pulled high via 10kΩ to 3.3V.
I²C / TWI0: PA_10 (Pin 28) = SCL, PA_11 (Pin 34) = SDA. 2kΩ pull-ups to 3.3V on both lines.
JTAG: ICE-1000 compatible 14-pin header. TDI/TCK/TMS direct, TDO via 22Ω, TRST via 4.7kΩ pull-down to GND. VDDIO on header pulled up via 4.7kΩ to 3.3V. EMU left unconnected.
GPIO LEDs: Five LEDs on PA_00–PA_04 (Pins 14/15/16/18/19), each with a series current limiting resistor.
HADC pins (81–84): All tied directly to GND, unused.
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My specific concerns are:
1. Power sequencing — does the ADSP-21565 have hard sequencing requirements between the 1.1V, 1.8V, and 3.3V rails, and does a passive approach satisfy them?
2. Are there any issues with the single-ended preamp into the ADAU1761 differential input as described above?
3. Any general errors or omissions I may have missed across any of the three pages.
I'm happy to share the schematic PDF with anyone willing to take a look. Thank you in advance.
