DMC pin remap

Hi,

There is no requirement to configure DDR byte swapping for the DDR data bus through software or DMC registers. The DDR interface works correctly as long as the DQ signals are connected to the proper DQS lines.

Please refer EE-418 using the below link for ADSP-2156x Board Design Guidelines for Dynamic Memory Controller
www.analog.com/.../ee418v02.pdf

Regards,
Nandini C

Thank you for the prompt reply NandiniC .  EE-418 says "Within a byte lane, data bits can be swapped, with the exception of the lowest order bit (for example, DQ0 should be connected to DQ0 of the processor if lane swapping is not done)" in the section discussing PCB trace routing.  This is how the ADSP-21569 SOM evaluation module is designed.  Can you please direct me to the location in the SOM board support package firmware where this is configured?

Hi,

The preload code is used during debug sessions, while the Init code is used during the boot process to configure the CGU and DMC.

For the DMC configuration, please refer the below initcode project from the installation path:
<Installation path>:\analog\cces\3.0.3\SHARC\ldr\init_code\2156x_Init\21569_init

You can find the files "adi_dmc_2156x_config.c" and "adi_dmc.c" in the 21569_init project for the DMC configuration.

Regards,
Nandini C

Thank you NandiniC .  I'm familiar with the files you referenced.  However, I do not see the lines of code or registers responsible for the DMC data bus bit swapping.  Can you please provide exact lines numbers in the example DMC configuration files where I can find the DMC data bus bit swapping?  If you prefer, please provide the names of the registers responsible for the DMC data bus bit swapping within the Hardware Reference Guide.

Hi,

Apologies for the confusion

The DMC data bus bit swapping supported on the ADSP-21569 is handled as a PCB routing/layout feature and does not require any dedicated software configuration or DMC remap registers.

As described in the EE-418 application note hardware design guidelines, entire byte lanes can be swapped provided the associated DQ, DQS, and DM signals are swapped together. Additionally, within a byte lane, DQ bits may also be reordered to simplify PCB routing and improve trace matching.

The DDR/DMC schematics can be referred to verify how signals such as DQ0, DQ1, DQ2, DQS, and DM are routed between the ADSP-21569 and the DDR memory device, including any supported bit swapping or reordering implemented in the hardware design.
Can you please refer the " DDR3 Interface" in the ADSP-SC59x schematics files. Please find the below link,
https://www.analog.com/media/en/technical-documentation/eval-board-schematic/ev-sc594-som-schematic.pdf

Because this flexibility is inherently supported by the DDR interface hardware, there are no dedicated DMC remap registers defined in the Hardware Reference Guide, and no corresponding remap configuration code is present in the BSP or DMC initialization files.

The DMC initialization code mainly configures DDR timing, refresh, calibration, and memory interface parameters.

Regards,
Nandini C

Thanks, I understand now.