Hardware Compatibility between ADSP-21569, ADSP-21593 and ADSP-21835

From what I can see, Change Mode from 001 to 101, use SFDP flash and it should work without the extra PA assignments. Please confirm.

Hi Al,

ADSP-21834/5 is layout compatible with ADSP-21566/7/9 and ADSP-21593. It is pin compatible with ADSP-21593 BGA package except for newly added power pin for PLL power domain(VDD_FPLLANA).

ADSP-21834/21835 processor GPIO multiplexing scheme is identical to that of the ADSP-21566, ADSP-21567, ADSP-21569, and ADSP-21593 processors.

For detailed information about the differences in the processor families, see the processor-specific data sheet and hardware reference manual.

Regards,
Nandini C

Hi Nandini

If you are using BMODE = 001 in the original design, it is not a drop in pin compatible part. It will try to Boot from SPI1 instead of SPI2 where the original flash is located. I would argue that  PA_00 thru PA_05 are less useful for alternate functions in most designs, therefore changing to BMODE 101 (xSPI) is usually best. 

This means that you need to pullup BMODE2 for 21835 and pulldown for 21569 or 21593. 

I am assuming that the bootloader reads 0x5A and can use a smaller I/O footprint if not using Octal FLASH. Octal Flash may be much faster, but it eats a lot of I/O for faster boot time.

Thank you for pointing out VDD_FPLLANA. I know the various datasheets and HRMs help, but they are certainly not light reading. I remember a document that addressed similar issues when the 21593 was released. I suggest a similar EE Note for this migration.

Regards,

Al

Hi Al,

If you are using BMODE = 001 in the original design, it is not a drop in pin compatible part. It will try to Boot from SPI1 instead of SPI2 where the original flash is located. I would argue that PA_00 thru PA_05 are less useful for alternate functions in most designs, therefore changing to BMODE 101 (xSPI) is usually best.
This means that you need to pullup BMODE2 for 21835 and pulldown for 21569 or 21593.
>> Yes, your understanding is correct.

I am assuming that the bootloader reads 0x5A and can use a smaller I/O footprint if not using Octal FLASH. Octal Flash may be much faster, but it eats a lot of I/O for faster boot time.
>> The xSPI controller boot supports booting from the NOR flash devices and Hyperflash devices using the xSPI controller. Like the legacy SPI, it supports booting from different flash devices provided by flash vendors.

Software-based discovery tries to read from the connected device by sending one-by-one, the following read commands until the flash device responds:
• Single SPI fast read command 0x3 with eight dummy cycles–one of the most common read commands supported by most flash devices.
• Octal read using the 0xEE/0x11 read command in OPI DTR mode with 20 dummy cycles–addresses Macronix octal flash devices configured in octal DTR mode.
• Hyperflash read sequence with 16 fixed latency cycles–addresses the Hyperflash devices that do not support SFDP.

For detailed information please refer “xSPI Controller Boot Mode” in the below linked HRM
www.analog.com/.../adsp-2183x-adsp-sc83x-hrm.pdf

Thank you for pointing out VDD_FPLLANA. I know the various datasheets and HRMs help, but they are certainly not light reading. I remember a document that addressed similar issues when the 21593 was released. I suggest a similar EE Note for this migration.
>> We will forward your suggestion to the concerned team for further evaluation.

Regards,
Nandini C

Hi Nandini, 

I wanted to follow up on this discussion on 21835 Boot mode b101.  I do see thru the ADI 21835 EVSOM that in this mode , the board is populated with an octal flash and I am sure this is tested for booting purposes.  On this xSPI (b101 boot mode), has a quad flash or a single data line flash been tested with actual flash chips (with the different data widths) ?   I only ask because this means the boot ROM for mode b101 is a little than usual to accommodate the different data widths.  Please confirm and thank you.

Regards,

Em Enrique

Hi Al,

As we mentioned earlier xSPI flash boot (SYS_BMODE 5) supports booting from hyperflash or legacy NOR flash devices using the xSPI peripheral, which includes all the bus modes from single STR to octal DTR and Hyperflash.

Please refer below application note “EE-450” which provides boot time estimation for ADSP-SC835 Processors for different boot modes. You can find more details about xSPI boot in the “xSPI Flash Boot” section.
https://www.analog.com/media/en/technical-documentation/application-notes/ee450v01.pdf

Regards,
Nandini C