Hi.
I have some questions about System Crossbars (SCB).
1. Where is the Sharc+ core SCB on the Figure 41-3: SCB Block Diagram?
2. How can C0_I get access to L1 according Figure 41-5: SCB Block Diagram - Interconnections?
3. On 41–12 says
S2 slave port of SHARCs is intended primarily for MDMA between the L1 of the 2 SHARCs. Hence, only the Max BW MDMA is given access to S2 ports while all others masters are given access to S1 port.This arrangement also means that S1 and S2 port now share the same address space as against the ADSP-2156x family of processors where an alias address space was maintained.
Can you explain about the sentence which contains "the 2 SHARCs"?
Can you explain about the sentence which contains "as against the ADSP-2156x family"?
4. How do SCB Arbitration work in the case which describe below.
My case is a simple interaction between the internal core action and external devices. So my program do some work which are based on data from external devices and internal state machine variables.
At the same time:
4.1. MDMA channels copy L1-to-L1 memory : from Source_MDMA_Destination_CORE_DataBufL1 to Destination_MDMA_Source_CORE_DataBufL1.
4.2. The SHARC+ copy L1-to-L1 memory : from Destination_MDMA_Source_CORE_DataBufL1 to Source_MDMA_Destination_CORE_DataBufL1.
4.3. Source_MDMA_Destination_CORE_DataBufL1and Destination_MDMA_Source_CORE_DataBufL1 have the same memory bank.
Do SCB Arbitration work every 32 bit L1 memory transfer or every L1 memory transfer which has some package length?
Best regards,
Daim
