DMA copy and copy working

Hi.

Yes both core and DMA are accessing the same L1 memory bank at the same time.

The core executed the main function of my device. Also I the core receiver and transfer data to/from the main function using LP and SPI. Also the core use both CRC units for checking CRC and MemDMA units for coping transfer data from the main function to transfer buffer and receiver buffer to receiver data for the main function.

The main function and receiver/transfer data to/from the main function using LP execute periodic by core time. So it are synchronized.

Executing the main function of my device and receiver/transfer data to/from the main function using SPI are asynchronicity.

The main function of my device are executed more often than SPI and more important. It must be real-time execution.

So I try to test some variants:

1. MemDMA coping of 4kBytes would be enable after executing the main function.

2. I don't use MemDMA and copy the data in a SEC nested software interrupt which has low priority than a SEC non-nested software interrupt of main function of my device. It's the old time-tested way.

Hi,

Thanks for the update.

Could you please confirm whether you are experiencing any data mismatch or data corruption issues due to the timing difference between the functions. If so, please provide detailed information about the exact issue so that we can assist you better on this.

Regards,
Nandini C

Hi.

Usually the core doesn't write to receiver data from SPI or LP except init.

Also SPI or LP doesn't write to transfer data.

I think any data mismatch or data corruption issues doesn't happen.

Regards,

Daim

Hi Daim,

Thank you for the clarification regarding the data ownership between core, SPI and LP.

Apologies that still we are not sure about your exact requirement. Could you please confirm whether you need any help regarding performance and timing when both the core and DMA access the same L1 memory bank. If not, please let us know your application with simple block diagram to understand better.

Regards,
Nandini C

Hi.

I think I miss something.

Does the SHARC+ core get access to the L1 memory thorough PM and DM buses without  the System Crossbars if the whole code of my program fit in the L1 memory and L1 cache turn off?

Regards,

Daim

Hi,

No, SHARC+ can’t access L1 memory without SCB. The System Crossbars (SCB) are the fundamental building blocks of the system bus interconnect. It allows concurrent data transfer between multiple bus masters and multiple bus slaves, providing flexibility and full-duplex operation.

We have application note EE-412, which discuss about the architectural features of the processors that contribute to the overall system bandwidth, system latencies, and optimization techniques:
https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.pdf

https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.zip

Regards,
Nandini C

Hi.

I think the application note EE-412 is very bad described my situation. I can't understand how much the arbitration works: only one time for the long MDMA's package or every times transfer/receiver some (one or MSIZE length) word from the whole long MDMA's package.

Can you explain my situation

1. MDMA_src and MDMA_dst win the arbitration to copy L1 to L1 many bytes (for example 32kBytes).

2. How the SHARC+ core get access to the L1 memory for instruction and data if MDMA early wins the arbitration to copy L1 to L1 many bytes and the memory for the SHARC+ core and MDMAs has same bank?

Does the SHARC+ core wait (stall)?

I can try to create the test project and to check with oscilloscope

I do my test program based on MDMA_Throughput example.

1. If only Sharc+ core copy 16384 bytes the execution time is about 11us.

2. If MDMA_src and MDMA_dst copy 16384 bytes and the Sharc+ core copy 16384 bytes at the same time the execution time is about 34us.

So it's understandable. But I can't understand how do SCB arbitration work? 

Hi!

I'm wrong about the time.

About my test program

1. The code is stored in L1 block0 and L1 block3.

2. The data of MDMA source/CORE destination is stored in L1 block2.

3. The data of MDMA destination/CORE source is stored in L1 block3.

4. First, MDMA is started to copy 16384 bytes from MDMA source memory to MDMA destination memory.

5. FLG1 is cleared.

6. Than the core immediately copy  16384 bytes from CORE source memory to CORE destination memory.

7. FLG1 is set.

CCLK is 1GHz.

The time between 5-7 is about 8.2us.

If MDMA is excluded than the time between 5-7 is about 6.8us.

Regards,

daim.