Post Go back to editing

CCES SRU configuration

Category: Software
Product Number: ADSP-21569
Software Version: ADSP-21569-SOM, CCES 3.0.3

I want to connect [ loudspeaker<-> EzKit <-> ADSP-21569-SOM <-> Brkout <-> AD2428WD1BZ <-> AD2428WC1BZ ] to make passthrough code.

In this connection, I set SRU init to connect [ ADSP-21569-SOM <-> Brkout <-> AD2428WD1BZ ].

This is my SRU init. Is there any error?

void SRU_Init(void)
{
/* Enable DAI pins */
*pREG_PADS0_DAI0_IE = 0x1ffffe;
*pREG_PADS0_DAI1_IE = 0x1ffffe;

/*==========================================================================
* A2B Interface (DAI0) - DSP is Master
* DAI0_PIN02: BCLK output to AD2428
* DAI0_PIN03: SYNC output to AD2428
* DAI0_PIN04: DTX0 input from AD2428
*========================================================================*/

/* PCG0 BCLK -> DAI0_PIN02 (output to A2B) */
SRU(PCG0_CLKA_O, DAI0_PB02_I);
SRU(HIGH, DAI0_PBEN02_I); /* Enable output */

/* PCG0 SYNC -> DAI0_PIN03 (output to A2B) */
SRU(PCG0_FSA_O, DAI0_PB03_I);
SRU(HIGH, DAI0_PBEN03_I); /* Enable output */

/* DAI0_PIN04 -> SPORT0A Data Input (A2B DTX0) */
SRU(DAI0_PB04_O, SPT0_AD0_I);
SRU(LOW, DAI0_PBEN04_I); /* Input */

/* PCG0 BCLK -> SPORT0A Clock */
SRU(PCG0_CLKA_O, SPT0_ACLK_I);

/* PCG0 SYNC -> SPORT0A Frame Sync */
SRU(PCG0_FSA_O, SPT0_AFS_I);

/*==========================================================================
* DAC Interface (DAI1) - DAC is Master (existing setup)
* DAI1_PIN05: BCLK from DAC
* DAI1_PIN04: FS from DAC
* DAI1_PIN01: Data to DAC
*========================================================================*/

/* DAC BCLK input */
SRU2(LOW, DAI1_PBEN05_I);

/* DAC BCLK -> SPORT4A and SPORT4B Clock */
SRU2(DAI1_PB05_O, SPT4_ACLK_I);
SRU2(DAI1_PB05_O, SPT4_BCLK_I);

/* DAC FS input */
SRU2(LOW, DAI1_PBEN04_I);

/* DAC FS -> SPORT4A and SPORT4B Frame Sync */
SRU2(DAI1_PB04_O, SPT4_AFS_I);
SRU2(DAI1_PB04_O, SPT4_BFS_I);

/* SPORT4A Data -> DAC */
SRU2(SPT4_AD0_O, DAI1_PB01_I);
SRU2(HIGH, DAI1_PBEN01_I); /* Enable output */

/* ADC Data -> SPORT4B (for RX) */
SRU2(DAI1_PB06_O, SPT4_BD0_I);
SRU2(LOW, DAI1_PBEN06_I); /* Input */

/* DAC BCLK -> ADC (for DAC clock reference) */
SRU2(DAI1_PB05_O, DAI1_PB12_I);
SRU2(HIGH, DAI1_PBEN12_I);

/* DAC FS -> ADC FS */
SRU2(DAI1_PB04_O, DAI1_PB20_I);
SRU2(HIGH, DAI1_PBEN20_I);
}

Thread Notes

Parents
  • Hi,

    We have reviewed the SRU configured you shared, and it seems that there is no issue in the SRU configuration. As you are using DAI1_PIN01, please modify the below snippet to enable DAI0/DAI1 Pin1.

    Please note that bit 0 in PADS0_DAI0_IE/PADS0_DAI1_IE register is used to enable the DAI0/DAI1 Pin1 and bit 20 is reserved.

    *pREG_PADS0_DAI0_IE = 0x0fffff;
    *pREG_PADS0_DAI1_IE = 0x0fffff;

    Regards,
    Nandini C

Reply
  • Hi,

    We have reviewed the SRU configured you shared, and it seems that there is no issue in the SRU configuration. As you are using DAI1_PIN01, please modify the below snippet to enable DAI0/DAI1 Pin1.

    Please note that bit 0 in PADS0_DAI0_IE/PADS0_DAI1_IE register is used to enable the DAI0/DAI1 Pin1 and bit 20 is reserved.

    *pREG_PADS0_DAI0_IE = 0x0fffff;
    *pREG_PADS0_DAI1_IE = 0x0fffff;

    Regards,
    Nandini C

Children
No Data