ASRC 16 Bit left justified to I2S

Hey together, 

I have another question regarding the SPORTs and the ASRC of the ADSP-21569. Maybe you can help. So far I am able to receive and transmit data via SPORT + DMA while running the ADSP als clock master. I also tried it by using the internal clock for the SPORTs as well as the PCGA as clock source. Everything fine so far. Now I am trying to get the ASRCs running. Here I'm a bit lost and I get only some crappy noise out of the DAC.

My plan is the following: 

The first question would be: 

- Q1: Is it really required to route the CRS outputs of the PCGA to a DAI1 PinBuffer? Is there no internal way to route the signals from PCGA to DAI1? 

- Q2: How should the configuration of the ASRC look like? What is right in my setup and what is wrong?

- Q3: When I am using the PCGA as clock source for the SPORTs, is the "nClockRatio" in the adi_sport_ConfigClock() required? 

Below is my code for the ASRC and the SPORT4A. Excuse by rought code, it is really hardcoded stuff but it is just for evaluation purpose.

#define COUNT 128
ADI_CACHE_ALIGN static int   int_SP4ABuffer0[COUNT];
ADI_CACHE_ALIGN static int   int_SP4ABuffer1[COUNT];

ADI_PDMA_DESC_LIST iSRC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP4A;
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static ADI_SPORT_HANDLE hSPORTDev4ARx; //ASRC RX

/*
Static Code for all other SPORTs and DMAs ...
*/


int SPU_init(void){
    if(adi_spu_Init(0, SpuMemory, NULL, NULL, &ghSpu) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to initialize SPU service\n");
		return FAILED;
    }

    /* Make SPORT 3A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_3A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT3A\n");
		return FAILED;
    }

    /* Make SPORT 3B to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_3B_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT3B\n");
		return FAILED;
    }

    /* Make SPORT 4A to generate secure transactions */
    if(adi_spu_EnableMasterSecure(ghSpu, SPORT_4A_SPU, true) != ADI_SPU_SUCCESS)
    {
    	REPORT_ERROR("Failed to enable Master secure for SPORT4A\n");
		return FAILED;
    }

    return SUCCESS;
}

static void PCG_init(void){
	ADI_PCG_CLK_INFO gClkInfoA;
	gClkInfoA.eClkInput = ADI_PCG_CLK_SCLK0;               /* Clock Source */
	gClkInfoA.nDiv = OUTPUT_PCG_CLOCK_DIV;               /* Clock Divisor */
	gClkInfoA.bExternalTrigger = false;                    /* External Trigger */

	ADI_PCG_FS_INFO gFsInfoA;
	gFsInfoA.eClkInput = ADI_PCG_FS_SCLK0;                 					/* Clock Source */
	gFsInfoA.nDiv = (OUTPUT_PCG_CLOCK_DIV)*(ADI_SPORT0A_CTL_SLEN + 1)*(2);	/* Frame Sync Divisor */
	gFsInfoA.nPulseWidth = (gFsInfoA.nDiv)/2;              					/* Pulse Width */
	gFsInfoA.nPhase = (OUTPUT_PCG_CLOCK_DIV)/2;                  			/* Phase */
	gFsInfoA.bExternalTrigger = false;                     					/* External Trigger */
	gFsInfoA.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL; 					/* Bypass Mode */

	adi_pcg_Init(ADI_PCG_DEV_A,&gClkInfoA,&gFsInfoA);

}

static int ASRC_init(void){
	ADI_ASRC_RESULT eAsrcResult = ADI_ASRC_FAILED;
	eAsrcResult = adi_asrc_Open(1u,                   /* Block number */
								0u,                   /* Device number */
								gAsrcMem,             /* Pointer to Memory */
								ADI_ASRC_MEMORY_SIZE, /* Memory Size */
								&hAsrc);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Open ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}
	eAsrcResult = adi_asrc_SetSerialFormat(hAsrc, ADI_ASRC_INPUT_16BIT_RIGHT_JUSTIFIED, ADI_ASRC_OUTPUT_I2S, ADI_ASRC_WORD_LENGTH_24);

    eAsrcResult = adi_asrc_RegisterCallback(hAsrc,AsrcCallback,NULL);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Register callback for ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}

	eAsrcResult = adi_asrc_Enable(hAsrc,true);
	if(eAsrcResult != ADI_ASRC_SUCCESS)
	{
		REPORT_ERROR("Could not Enable ASRC  0x%08X\n", eAsrcResult);
		return FAILED;
	}

	return SUCCESS;
}

static void PrepareDescriptors (void)
{

	iDESC_LIST_1_SP3A.pStartAddr	= (int *)int_SP0ABuffer1; /* Data array */
	iDESC_LIST_1_SP3A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_1_SP3A.XCount		= COUNT;
	iDESC_LIST_1_SP3A.XModify		= 4; /* Increase data address */
	iDESC_LIST_1_SP3A.YCount		= 0;
	iDESC_LIST_1_SP3A.YModify		= 0;
	iDESC_LIST_1_SP3A.pNxtDscp		= &iDESC_LIST_2_SP3A;

	iDESC_LIST_2_SP3A.pStartAddr	= (int *)int_SP0ABuffer2; /* Data array */
	iDESC_LIST_2_SP3A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iDESC_LIST_2_SP3A.XCount		= COUNT;
	iDESC_LIST_2_SP3A.XModify		= 4; /* Increase data address */
	iDESC_LIST_2_SP3A.YCount		= 0;
	iDESC_LIST_2_SP3A.YModify		= 0;
	iDESC_LIST_2_SP3A.pNxtDscp		= &iDESC_LIST_1_SP3A; /* Points to the first descriptor */

	iSRC_LIST_1_SP4A.pStartAddr	= (int *)int_SP4ABuffer0; /* Data array */
	iSRC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_1_SP4A.XCount		= COUNT;
	iSRC_LIST_1_SP4A.XModify		= 4; /* Increase data address */
	iSRC_LIST_1_SP4A.YCount		= 0;
	iSRC_LIST_1_SP4A.YModify		= 0;
	iSRC_LIST_1_SP4A.pNxtDscp		= &iSRC_LIST_2_SP4A;

	iSRC_LIST_2_SP4A.pStartAddr	= (int *)int_SP4ABuffer1; /* Data array */
	iSRC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
	iSRC_LIST_2_SP4A.XCount		= COUNT;
	iSRC_LIST_2_SP4A.XModify		= 4; /* Increase data address */
	iSRC_LIST_2_SP4A.YCount		= 0;
	iSRC_LIST_2_SP4A.YModify		= 0;
	iSRC_LIST_2_SP4A.pNxtDscp		= &iSRC_LIST_1_SP4A; /* Points to the first descriptor */
}

static void SPORTCallback(void *pAppHandle,uint32_t nEvent,void *pArg){
	int i;
    /* CASEOF (event type) */
    switch (nEvent){
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        	adi_gpio_Toggle(GPIO_DAC_PORT,GPIO_DAC_PIN);
        break;
        default:
        break;
    }
}


static void SPORTCallbackASRC(void *pAppHandle, uint32_t nEvent, void *pArg){
	int i;
    /* CASEOF (event type) */
    switch (nEvent){
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
        	adi_gpio_Toggle(GPIO_ASRC_PORT,GPIO_ASRC_PIN);
			#if FORWARD_ASRC
			TestCallbackCount +=1;
			AsrcCallbackCount +=1;
			if(AsrcCallbackCount==1){
				for(i=0;i<COUNT;i+=2){
					int_SP0ABuffer1[i]=int_SP4ABuffer0[i];/*Copy ASRC Buffer to DAC */
					int_SP0ABuffer1[i+1]=int_SP4ABuffer0[i+1];/*Copy ASRC Buffer to DAC */
					++copyCount;
				}
			}
			if(AsrcCallbackCount==2){
				for(i=0;i<COUNT;i+=2){
					int_SP0ABuffer2[i]=int_SP4ABuffer1[i];/*Copy ASRC Buffer to DAC */
					int_SP0ABuffer2[i+1]=int_SP4ABuffer1[i+1];/*Copy ASRC Buffer to DAC */
					++copyCount;
				}
				AsrcCallbackCount=0;
			}
			#endif
        break;
        default:
        break;
    }
}

int Sport_init(bool slave, bool rxCH12, bool rxCH34){

	PCG_init();

    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 3a */
	eResult = adi_sport_Open(SPORT_DEVICE_3A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_I2S_MODE, SPORTMemory3A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev3ATx);
	/* Try to enable the clock */
	adi_sport_ConfigClock(hSPORTDev3ATx,39,false,false,false);
	adi_sport_ConfigFrameSync(hSPORTDev3ATx,ADI_SPORT0A_CTL_SLEN,false,false,false,true,false,false);


	/* Open the SPORT Device 3B*/
	eResult = adi_sport_Open(SPORT_DEVICE_3B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory3B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev3BRx);
	adi_sport_ConfigClock(hSPORTDev3BRx,39,false,false,false);
	adi_sport_ConfigFrameSync(hSPORTDev3BRx,ADI_SPORT0A_CTL_SLEN,false,false,false,true,false,false);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev3BRx,SPORTCallback,NULL);
	eResult = adi_sport_RegisterCallback(hSPORTDev3ATx,SPORTCallbackTx,NULL);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Open the SPORT Device 4A ASRC */
	eResult = adi_sport_Open(SPORT_DEVICE_4A, ADI_HALF_SPORT_A, ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory4A, ADI_SPORT_MEMORY_SIZE, &hSPORTDev4ARx);
	CHECK_RESULT(eResult);
	adi_sport_ConfigData(hSPORTDev4ARx, ADI_SPORT_DTYPE_SIGN_FILL, 31, false, true, false);
	adi_sport_ConfigClock(hSPORTDev4ARx, 39, false, false, false);
	adi_sport_ConfigFrameSync(hSPORTDev4ARx, 31, false, false, false, false, false, false);
	eResult = adi_sport_RegisterCallback(hSPORTDev4ARx, SPORTCallbackASRC, NULL);
	ASRC_init();
	eResult = adi_sport_DMATransfer(hSPORTDev4ARx,&iSRC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev3BRx,&iSRC_LIST_1_SP3B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	eResult = adi_sport_DMATransfer(hSPORTDev3BRx,&iSRC_LIST_1_SP3B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_SEC);

	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev3ATx,&iDESC_LIST_1_SP3A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);

	/*Enable the Sport Device 4B */
	eResult = adi_sport_Enable(hSPORTDev3BRx,true);
	/*Enable the Sport Device 3a */
	eResult = adi_sport_Enable(hSPORTDev3ATx,true);
	/*Enable the Sport Device 4a */
	eResult = adi_sport_Enable(hSPORTDev4ARx,true);
	return eResult;
}

int main(int argc, char *argv[])
{
	/**
	 * Initialize managed drivers and/or services that have been added to 
	 * the project.
	 * @return zero on success 
	 */
	adi_initComponents();
	adi_pwr_SetClkOutSelectRegister(ADI_PWR_CGU0, ADI_PWR_CLKOUT_CGU0_CCLK0);
	/* Begin adding your custom code here */
	ADI_UART_RESULT    eUartResult;
	ADI_TWI_RESULT 	eTwiResult;
    if(result == SUCCESS){
    	result = ADAU1372_init(!slave);
    	if(result == SUCCESS){
    		result = Sport_init(slave, rxCH12, rxCH34);
    		if(result == SUCCESS){
    		
    		}
    	}
    }
    while(1){

	}
//	return 0;
}

Thanks a lot in advance. 

Best regards,

Eric