Hello,
We are currently designing a daughter board using the EV-21569-SOM.
The website currently only provides Rev A schematics, whilst the board we purchased is Rev C, and we noticed several differences.
Would it be possible to get our hands on the newer schematics, and possibly a 3D file of the board to check clearance?
I noticed a thread that had a similar request (https://ez.analog.com/dsp/software-and-development-tools/cces/f/q-a/590542/ev-21569-som-rev-c-and-ev-somcrr-ezkit-rev-d-do-not-work-with-bsp), but the schematics weren't shared publicly.
If you have any other notes or files concerning the changes I would also happily take them, especially since the current BSP apparently does not communicate well with the clock generator, which is a component that we would like to exploit.
While I am at it, I would also like to confirm the maximum SPI slave clock speeds for the ADSP-2156x.
The datasheet mentions f_SPICLKEXT is 62.5 MHz maximum for receiving data with an external clock.
We initially intended to use a 100 MHz clock (from the aforementioned generator) for an ADC to get 8 datapoints per period but we seemingly have to settle with 50 or 62.5 (for 4 or 5 datapoints respectively, which isn't bad either, but more=better).
Best regards,
Arcady Ruvidic
