adsp21569 sport switch internal/external clock

Hi,

To switch from the internal clock to the external clock during the operation of the SPORT interface, when the internal clock is initially set by default (via adi_sport_ConfigClock - bUseIntlClock = 1), the configuration can be modified by setting bUseIntlClock = 0 to select the external clock source.

The following sequence of steps can be executed before switching to the external clock:

1. Disable the SPORT:
First, disable the SPORT device for data transfer by invoking the adi_sport_Enable API with a parameter of "false". This function will suspend the device's operation.

2. Adjust the SRU (Signal Routing Unit) Configuration:
Ensure proper routing of the SPORT signals in both internal and external clock configurations:

Also, please refer to the ezone thread below, which discusses the steps to follow when changing SRU connections during runtime. It might be helpful.
https://ez.analog.com/dsp/sharc-processors/f/q-a/63262/adsp-21469-multiple-clocking-options

3. Configure External Clock and Frame Sync:
Next, configure the external clock by setting adi_sport_ConfigClock - bUseIntlClock = 0, and configure the frame sync by invoking adi_sport_ConfigFrameSync - bInternalFS = 0 to use the external frame sync.

4. Enable Data Transfer:
After configuring the clock and frame sync, use the adi_sport_DMATransfer API to submit the buffer for both transmit (Tx) and receive (Rx) operations. Finally, enable the SPORT interface for data transfer by setting adi_sport_Enable to "true".

For more information about the API's, please refer the below CCES help path:
CrossCore® Embedded Studio 3.0. > System Run-Time Documentation > System Services and Device Drivers > ADSP-21569 Family (SHARC+ Core) API Reference > Modules > SPORT Device Driver

Regards,
Nandini C

Hello NandiniC

Thank you very much for the response.

For our use case, the internal clock is from PCG but not sport self, and the external clock is from out of ADSP21569(eg. external A2B clock).

Currently, I use the PCG configuration to change the clock which is from internal PCG or the clock of the external A2B. For Sport, they should be external clocks. I understand that I should not need to call the adi_sport_CofigClock interface to set bUseIntlClock = 1 or bUseIntlClock=0. Do I understand correctly?

1.  Disable the SPORT:  ---> got it.

2.  Adjust the SRU (Signal Routing Unit) Configuration:  ---> got it, will look into it .

3.  Configure External Clock and Frame Sync.---> for my above use case, do I need this step?

4. Enable Data Transfer:---> got it.

Hi,

Yes, your understanding is correct. As PCG clock considered as external clock, there's no need to call the adi_sport_ConfigClock API to switch the clock's.

You can follow the below steps:
1. Disable the SPORT.
2. Adjust the SRU (Signal Routing Unit) Configuration.
3. Enable the Data Transfer and SPORT.

Regards,
Nandini C

Hi NandiniC

Thank you for the clarifying.

For Step 4: "After configuring the clock and frame sync, use the adi_sport_DMATransfer API to submit the buffer for both transmit (Tx) and receive (Rx) operations. Finally, enable the SPORT interface for data transfer by setting adi_sport_Enable to "true"."

I have further question: "After configuring the clock and frame sync" ,  do I need to do anything special? I In my using case, the clock is either the PCG clock (divided by the external crystal to get 24.576MHz) or the 24.576MHz provided by the external A2B master device. In addition to adjusting the SRU mapping, do I need to do anything special? thank you!

best regards

Alisa

Hi,

No, as stated in the Ezone link below, you can follow the specified conditions to manage the clock switching process.
ADSP 21469 multiple clocking options 

If you experience any issues while switching the clock, please share the details with us, and we will assist you.

Regards,
Nandini C

Hi Nandini C

Yes, I did encounter some problems:

case1：

I did the step2， the experience result is as below.  I suspect that when switching, the clock is offset or the sport DMA does not know how to recognize the first slot data coming from the A2B bus. Could you give some advice on how to sync the clock again after switching it repeatedly?

By default, my system uses the external A2B master clock as the startup clock. The system can start up and output the expected audio sound. Then I switch to the PCG clock to keep the system sport running, and the task can also run normally. Then I switch to the external A2B master clock again. At this time, the audio output slot will be shifted. For example, the output is 1KHz when it is powered on. When it switches to the A2B master clock for the second time, the audio output may be 2KHz. Regardless of 1KHz or 2KHz, it is the slot data transmitted by the A2B master through the A2B bus.

case 2：

currently  when I called the adi_sport_Enable API, the system will go to reset continue, could you please share the register configration code  for  replacing called adi_sport_Enable api , I should config sport0A/0B/3B/5A/6B/7A/7B.  could I called the two below for sport enable or disable?

Hi,

Regarding Case1:
>> Could you please confirm the sampling frequency you are currently using. Additionally, ensure that the sampling frequency is properly re-configured on the A2B master clock side when switching from the PCG clock to the A2B master clock. It is important to verify that all configurations on the A2B master side are correctly updated.

Furthermore, could you provide the probe images of CLK, FS, and Data for all instances of clock switching in order to verify the data. Also, please confirm whether you are using the I2S channel or a multichannel configuration.

Regarding Case2:
>> You have mentioned that the system will go to reset continue, when you call the adi_sport_Enable API. Could you please clarify whether this reset issue occurs when switching from the PCG clock to the A2B master clock, or if it happens during the initial switch from the A2B master clock to the PCG clock.

Additionally, the Sport Global Enable API is used to enable SPORT transfers globally at the same time. Please ensure that all SPORTs in the group have the same data, clock, and frame sync configuration. While enabling multiple SPORTs need to be synchronized so that all of them start and/or end at the same time.

For reference, you can refer to Global SPORT example in ADSP-2156x BSP path given below.
[Installation directory]:\Analog Devices\EV-2156x_EZ-KIT-Rel1.0.1\EV-2156x_EZ-KIT\Examples\drivers\adc
You can refer to the example and you can modify as per your requirement.

Also, please refer to the "Grouping of SPORTs" [Pg:23-44] and "Programming Global SPORT Groups" [Pg:23-50] for more clarity on SPORT grouping and Global Enable methods in the HRM.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2156x_hwr.pdf

Regarding Case3:
>> If you have declared a 2D buffer, you need to use the adi_sport_2DDMATransfer API, providing the YCount and YModify in the descriptor list. If you are using a 1D buffer, you can use the adi_sport_DMATransfer API instead.

Additionally, please confirm that when switching between clocks, the buffer configuration must be properly updated on both ends to ensure proper functionality.

Regards,
Nandini C

Hello  Nandini C

Regarding Case 1 

 Could you please confirm the sampling frequency you are currently using. Additionally, ensure that the sampling frequency is properly re-configured on the A2B master clock side when switching from the PCG clock to the A2B master clock. It is important to verify that all configurations on the A2B master side are correctly updated.

Furthermore, could you provide the probe images of CLK, FS, and Data for all instances of clock switching in order to verify the data. Also, please confirm whether you are using the I2S channel or a multichannel configuration.

==>The A2B master clock is fixed from the master device, I just connected /disconnected A2B port, from the log, A2B slave should be correctly identified and re-configured by A2B master device when connected.  I am using a multichannel configuration.

Regarding Case2:
 You have mentioned that the system will go to reset continue, when you call the adi_sport_Enable API. Could you please clarify whether this reset issue occurs when switching from the PCG clock to the A2B master clock, or if it happens during the initial switch from the A2B master clock to the PCG clock.

==>Call the adi_sport_Enable API will go to reset continue at both switch cases(the PCG to A2B master clock and A2B master clock to PCG).

      I am not sure that the issue is related  if(pDevice->bProgress == true), if the dma is transfering data in progress,  I call 

Regarding Case3:
If you have declared a 2D buffer, you need to use the adi_sport_2DDMATransfer API, providing the YCount and YModify in the descriptor list. If you are using a 1D buffer, you can use the adi_sport_DMATransfer API instead.

==>So I can use the adi_sport_2DDMATransfer API for re start DMA data transfer, am I right? 

Additionally, please confirm that when switching between clocks, the buffer configuration must be properly updated on both ends to ensure proper functionality.

==>Could you share more info about which buffer configuration need to be updated, can I update with the Sport initializer value to set?

Thank you

Hi,

Apologies for delayed response.

Regarding "The A2B master clock is fixed from the master device, I just connected /disconnected A2B port, from the log, A2B slave should be correctly identified and re-configured by A2B master device when connected. I am using a multichannel configuration."
>>> Could you please share the clock configurations (Clock, Frame Sync ) for the A2B master, along with the corresponding probe images?

Regarding "Call the adi_sport_Enable API will go to reset continue at both switch cases(the PCG to A2B master clock and A2B master clock to PCG)."
>>>To replicate the issue on our side, we have attached the example code that demonstrates audio loopback using two SPORTs (SPORT4A and SPORT4B) in multichannel mode. In this example, we use an external clock with the PCGC, routing both the clock and frame sync to the SPORT through the SRU_Init() function. We enable the SPORT configuration and verify that the audio output works as expected.

Next, we disable the SPORT DMA using the adi_sport_StopDMATransfer API, followed by disabling the SPORT with the adi_sport_Enable API. Afterwards, we switching to a different external clock source (PCGD) for the SPORT, initialize the PCG_init2 and SRU2_init functions for routing, and re-enable both the SPORT DMA transfer and SPORT using the adi_sport_StopDMATransfer and adi_sport_Enable APIs. It works as expected on the ADSP-21569 EZ-KIT.

8838.Audio_Loopback_TDM.zip

Please take this example code as a reference and modify it accordingly to your application.

Could you please confirm which APIs you are using to switch from the PCG clock to the A2B master clock? Are they the same as those mentioned above, or are there other different APIs in use?

Regarding "So I can use the adi_sport_2DDMATransfer API for re start DMA data transfer, am I right? "
>>> You can use either the adi_sport_2DDMATransfer or adi_sport_DMATransfer APIs to restart the DMA data transfer. Depending on your application, you can choose the appropriate API.

Regarding "Could you share more info about which buffer configuration need to be updated, can I update with the Sport initializer value to set?"
>>>When switching between clocks, it’s essential to ensure that the buffer configuration is correctly updated on both ends. Could you also confirm that the buffer configuration for the SPORT is properly initialized and that the DMA settings are correctly configured within the APIs?

Regards,
Nandini C