It is well documented that when booting from an external SPI host (boot mode 0b10) that the SPI master should transmit bytes one at a time and check SPI2_RDY after each byte. I have a few questions related to how SPI2 is configured when operating in this mode:
1) What is the actual size of the ADSP's SPI2 receive buffer when operating in this boot mode?
2) Is a "ping pong" buffer strategy used? I.e. are there actually 2 receive buffers where one is getting read by the ADSP chip and the other is being written to by the SPI host, and then they are swapped once the buffer being written is full
2) At what threshold is SPI2_RDY deasserted? i.e. when the receive buffer is 50% full? 75% full?
Thanks in advance for your help.