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Questions regarding the implementation of SPI2 external host boot mode (boot mode 0b10)

Category: Hardware
Product Number: ADSP-21569

It is well documented that when booting from an external SPI host (boot mode 0b10) that the SPI master should transmit bytes one at a time and check SPI2_RDY after each byte. I have a few questions related to how SPI2 is configured when operating in this mode:

1) What is the actual size of the ADSP's SPI2 receive buffer when operating in this boot mode?

2) Is a "ping pong" buffer strategy used? I.e. are there actually 2 receive buffers where one is getting read by the ADSP chip and the other is being written to by the SPI host, and then they are swapped once the buffer being written is full

2) At what threshold is SPI2_RDY deasserted? i.e. when the receive buffer is 50% full? 75% full?

Thanks in advance for your help.

  • Hi Michael,

    1)What is the actual size of the ADSP's SPI2 receive buffer when operating in this boot mode?
    >>> As mentioned in Pg: 657 of  ADSP-21569 HRM, the size of the receive FIFO is 8 if the word size is 8-bit, or the size is 4 if the word size is 16-bit, or the size is 2 if the word size is 32-bit

    2)Is a "ping pong" buffer strategy used? I.e. are there actually 2 receive buffers where one is getting read by the ADSP chip and the other is being written to by the SPI host, and then they are swapped once the buffer being written is full
    >>>Yes, your understanding is correct.

    3)At what threshold is SPI2_RDY deasserted? i.e. when the receive buffer is 50% full? 75% full?
    >>> The SPI is configured to deassert the SPIx_RDY when the receive FIFO is filled to 75% or more.

    For more details, please refer the Slave boot mode section in HRM of ADSP-21569.
    https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2156x_hwr.pdf

    Regards,
    Nandini C