ADSP-21569 - Delay in SPI RX of 5x 32-bit words

Hi,

Could you please confirm whether you have enabled "DMA_CFG.SYNC" bit and "DMA_CFG.INT" bit. If not, Could you please try to enable the "DMA SYNC" bit, and "Peripheral Interrupt request" bit from "DMA_CFG" register.

It is important to synchronize between peripheral requests and DMA. Synchronizing allows programs to change the DMA_CFG.PSIZE between individual work units and, in some cases, work unit chains. This sync operation resets the FIFO pointers, avoiding misaligned access to the FIFO.

Also, could you please share us the below details to assist you further on this issue.
1. What is the SPI Clock? Is it provided by the Host to the Slave?
2. Could you verify the SCLK in your system to ensure it meets the specifications outlined in the datasheet?
3. Can you confirm whether the normal, Master Transmit Slave Receive(MOSI) operation functions correctly?
4. Are you experiencing the issue only in DMA Descriptor List mode? If so, could you test it in a different mode?
5. Have you configured the SPI delay register? If so, please try setting it to zero and observe the results.
6. Could you provide probe images of the MISO, MOSI, CLK, and SS signals?
7. Could you provide a detailed explanation of your application? A simple block diagram would be very helpful.

Also, we would suggest you refer the section "Configuring DMA Slave Mode Operation"[Page No:15–32] in ADSP-21569 Hardware reference Manual from the below link,
https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2156x_hwr.pdf

For more information, Please refer to the configuration register sections "DMA_CFG "[Page No: 27–50] in the above linked ADSP-21569 Hardware reference Manual.

Regards,
Nandini C

Hello Nandini, thank you for the quick response! I have attached a PDF here with the answers to most of these questions. I will capture traces for you ASAP. Please let me know if you need any clarifications and thank you in advance for the assistance.



PDF

Hi,

We understand that you can successfully transmit and receive data using the ADSP-21569 (MOSI). However, you’re having trouble correctly reading Sigma Studio data transferred from the slave to the master. Could you confirm if this understanding is correct.
Please clarify which SPI instances you are using for both the master and slave.

1. Confirm whether you are using SPI1 or SPI2. Your code is configured for SPI1, but the screenshot shows configuration for SPI2. Could you clarify this.
2. Your screenshot shows the SPI2_Delay register enabled with Lag, Lead, and Stop bits. Confirm whether you have disabled the Lag and Lead bits by programming the SPI_Delay register. Note that setting the SPI_DLY.STOP bit to 0 enables continuous operation of each SPI transfer.
3. Confirm whether you have protected the appropriate DMA channels in the DMA controller. If not, protect those channels using the System Protection Unit (SPU). For more details, refer to the System Protection Unit section in the ADSP-21569 hardware reference manual:
www.analog.com/.../adsp-2156x_hwr.pdf
4.In your code, the adi_spi_DMAWrite and adi_spi_DMARead functions use the same "hInfo" parameters for both read and write operations with identical slave configurations. Please ensure that you will use a SPI buffer according to Tx and Rx.
5. Ensure that the clock polarity (SPI_CTL.CPOL) and clock phase (SPI_CTL.CPHA) are identical for both the master and slave devices in the communication link.
6. Enable the receiver first to ensure proper synchronization.
7. Verify that the SPI clock speed is the same for both the transmitter and receiver sides, as this affects data transfer speed.
8. Make sure both the master and slave devices are configured with the same word size for correct operation.

Regards,
Nandini C