I am using SPORTs 0B, 1B, 6B, and 7B for ADC inputs. All ADCs receive the same TDM clocks, and their output data appears to be aligned when viewed with a logic analyzer, but for some reason SPORTS 1B and 7B require a frame delay of 0 while 0B and 6B require a frame delay of 1. Can anyone give some insight into why this is?
Thank you