MSIZE and PSIZE of DMA_CFG in Hardware Reference

Hi,

PSIZE determines the bus (Peripheral Bus) width between DMA module and peripheral. Whereas MSIZE determines the bus (Memory Bus) width between DMA module and processor memory.

Regarding "MSIZE"
>>>> Yes, your understanding is correct.

Regarding "PSIZE"
>>>> PSIZE can be configured to 4 or 8 bytes.

Regards,
Ranjitha R

But the SPIDMAMode_21569 example of ADSP-2156x_EZ-KIT-Rel1.0.1 set fields MSIZE and PSIZE to zero.

According Hardware Reference Revision 1.1, October 2022 MSIZE of DMA may have ONLY next values:

2 - 4 bytes

3 - 8 bytes

4 - 16 bytes

5 - 32 bytes
and PSIZE of DMA may have ONLY next values:

2 - 4 bytes

3 - 8 bytes

WHY?

At one point ADSP-2159x/ADSP-SC592/SC594 can use:

MSIZE: 1, 2, 4, 8, 16 or 32 bytes

PSIZE: 1, 2, 4, or 8 bytes

So I set MSIZE and PSIZE to zero value (1 byte). And my software work well.

So ADSP-2156x's HRM is wrong about MSIZE and PSIZE fields of DMA_CFG. But ADSP-2159x's HRM is right. And MSIZE and PSIZE fields of DMA_CFG ADSP-2156x can get

MSIZE: 1 (=0), 2 (=1), 4 (=2), 8 (=3), 16 (=4) or 32 (=5) bytes

PSIZE: 1 (=0), 2 (=1), 4 (=2) or 8 (=3) bytes

I tested my software when MSIZE=0 and PSIZE=0.

Hi,

The DMA_CFG.PSIZE parameter determines the width of the peripheral bus, offering with options of 1, 2, 4, or 8 bytes. It's important to note that this parameter must not exceed the maximum bus width set by the DMA_STAT.PBWID bit field due to the lack of support for burst transactions on the peripheral bus.

Likewise, the DMA_CFG.MSIZE parameter specifies both the size of the SCB bus and the minimum byte transfer per DMA request/grant. It provides choices of 1, 2, 4, 8, 16, or 32 bytes. If the MSIZE value exceeds DMA_STAT.MBWID, the SCB performs burst transfers equivalent to the MSIZE value.

Functionally, setting both MSIZE and PSIZE to 0 is feasible. Yet, for optimal performance/throughput in DMA, use the highest possible MSIZE value (32 bytes) for better average throughput. This results in a higher likelihood of uninterrupted sequential accesses to the target (memory), which is the most efficient for typical memory designs. So, we would suggest you to follow as per the information provided in HRM.

For more information, regarding performance, please refer the application note EE- 412 "ADSP-2156x SHARC+ Processor System Optimization Techniques" in the below link.
https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.pdf

Associated zip file can be found from below link.
https://www.analog.com/media/en/technical-documentation/application-notes/ee412v02.zip

Regards,
Ranjitha R

Hi.

I point that ADSP-2156x's HRM says that MSIZE can get 4, 8, 16 or 32 bytes and PSIZE can get 2 or 8 bytes.

Only it. So I think ADSP-2156x's HRM are explained non-available value of MSIZE and PSIZE fields. So you can create ticket in ADI bug system to fix ADSP-2156x's HRM.

From ADSP-2156x's HRM