Clarification on calculating SPDIF_TX_HFCLK_I clock speed required for 192KHz SPDIF transmission

Hi Michael,

Yes, the calculation seems correct. The high frequency clock HFCLK is use for the encoding the audio signal in S/PDIF transmitter. So, the transmitter needs to be configured for an over-sampling ratio of 256 x FS. Hence, for a specific frame sync (FS) frequency, HFCLK should be 256 x FS, and the bit-clock should be 64 x FS.

Sampling frequency: 192KHz
HF CLK    : 256 x FS = 256*192KHz = 49.152MHz
Bit clock    : 64 x FS   = 64*192KHz   = 12.288 MHz

Regards,
Ranjitha.R

Hi Ranjitha, thanks for the confirmation. May I ask where this is documented? I couldn't find it anywhere.

Hi Michael,

Please refer the application note(EE-266) which discusses briefly about SPDIF. The link is given below.
www.analog.com/.../ee.266.rev.2.08.07.pdf

Regards,
Ranjitha.R

Ranji, why is the only reference to this in an application note from 2007 about a processor from a different generation? Would it not be more useful to put a line of explanation in the hardware reference manual?

Hi Michael,

Thank you for pointing this. We will check internally and make sure to update the documentation in future.

Regards,
Ranjitha R

Thank you very much