Category: Hardware
Product Number: ADSP21569
I work with ADSP21569 to use ASRC.
I know that The ASRC can operate in TDM, I2S, left-justified, right-justified mode.
And I already test two situations.
1. I2S input mode with I2S output mode
2. TDM input mode with TDM output mode
But I want ASRC to work in TDM intput mode with I2S output mode, or I2S input mode with TDM output mode.
Here is the code for sru. checking the Ratio Register for ASRC, the rate is OK.
But in sport1a/1b the data is wrong!!!
// *
// * in to asrc
// * dante BCLK ---> DAI0_CRS_PB03_O ---> SRC0_CLK_IP_I / SRC1_CLK_IP_I / SRC2_CLK_IP_I / SRC3_CLK_IP_I
// * datne LRCLK ---> DAI0_CRS_PB04_O ---> SRC0_FS_IP_I / SRC1_FS_IP_I / SRC2_FS_IP_I / SRC3_FS_IP_I
// * in0(ch9-ch16) ---> DAI0_PIN01 ---> SRC0_DATA_IP_I
// * SRC0_TDM_IP_O ---> SRC1_DATA_IP_I
// * SRC1_TDM_IP_O ---> SRC2_DATA_IP_I
// * SRC2_TDM_IP_O ---> SRC3_DATA_IP_I
// bclk
SRU2 (LOW, DAI1_PB03_I);
SRU2 (LOW, DAI1_PBEN03_I);
SRU (DAI0_CRS_PB03_O, SRC0_CLK_IP_I);
SRU (DAI0_CRS_PB03_O, SRC1_CLK_IP_I);
SRU (DAI0_CRS_PB03_O, SRC2_CLK_IP_I);
SRU (DAI0_CRS_PB03_O, SRC3_CLK_IP_I);
// lrclk
SRU2 (LOW, DAI1_PB04_I);
SRU2 (LOW, DAI1_PBEN04_I);
SRU (DAI0_CRS_PB04_O, SRC0_FS_IP_I);
SRU (DAI0_CRS_PB04_O, SRC1_FS_IP_I);
SRU (DAI0_CRS_PB04_O, SRC2_FS_IP_I);
SRU (DAI0_CRS_PB04_O, SRC3_FS_IP_I);
// data in
SRU (LOW, DAI0_PB01_I);
SRU (LOW, DAI0_PBEN01_I);
SRU (DAI0_PB01_O, SRC0_DAT_IP_I);
SRU (SRC0_TDM_IP_O, SRC1_DAT_IP_I);
SRU (SRC1_TDM_IP_O, SRC2_DAT_IP_I);
SRU (SRC2_TDM_IP_O, SRC3_DAT_IP_I);
// * asrc ---> sport1A/sport1B
// * BCLK(外部) ---> DAI0_PIN03 ---> sport1A/sport1B BCLK ---> SRC0_CLK_OP_I / SRC1_CLK_OP_I / SRC2_CLK_OP_I / SRC3_CLK_OP_I
// * LRCLK(外部) ---> DAI0_PIN04 ---> sport1A/sport1B LRCLK ---> SRC0_FS_OP_I / SRC1_FS_OP_I / SRC2_FS_OP_I / SRC3_FS_OP_I
// * in0(ch9-ch10) ---> SRC0_DATA_OP_O ---> sport1AD0
// * in1(ch11-ch12) ---> SRC1_DATA_OP_O ---> sport1AD1
// * in2(ch13-ch14) ---> SRC2_DATA_OP_O ---> sport1BD0
// * in3(ch15-ch16) ---> SRC3_DATA_OP_O ---> sport1BD1
// bclk
SRU (DAI0_PB03_O, SPT1_ACLK_I);
SRU (DAI0_PB03_O, SPT1_BCLK_I);
SRU (DAI0_PB03_O, SRC0_CLK_OP_I);
SRU (DAI0_PB03_O, SRC1_CLK_OP_I);
SRU (DAI0_PB03_O, SRC2_CLK_OP_I);
SRU (DAI0_PB03_O, SRC3_CLK_OP_I);
// lrclk
SRU (DAI0_PB04_O, SPT1_AFS_I);
SRU (DAI0_PB04_O, SPT1_BFS_I);
SRU (DAI0_PB04_O, SRC0_FS_OP_I);
SRU (DAI0_PB04_O, SRC1_FS_OP_I);
SRU (DAI0_PB04_O, SRC2_FS_OP_I);
SRU (DAI0_PB04_O, SRC3_FS_OP_I);
// data out
SRU (SRC0_DAT_OP_O, SPT1_AD0_I);
SRU (SRC1_DAT_OP_O, SPT1_AD1_I);
SRU (SRC2_DAT_OP_O, SPT1_BD0_I);
SRU (SRC3_DAT_OP_O, SPT1_BD1_I);
