ADSP-21569
Recommended for New Designs
Reaching speeds of up to 1 GHz, the ADSP-2156x processors are members of the SHARC® family of products. The ADSP-2156x processor is based on the SHARC...
Datasheet
ADSP-21569 on Analog.com
I want ONLY use S/PDIF Transmitte in adsp21565 and i encount some issue .
the route: sport3B(tx)---------SPDIF TX0 (tx) ---------DAI0_PIN08(TX)
1 the next picture about my pcg B config and it's right?


nDIV=2 ,ADI_PCG_CLK_EXT=24.576MHz(DAI0_PIIN03)
2 the next picture about my SPDIF TX0 config and it's right?


3 the next picture about my SPOTRT 3b config and it's right?



AND NOW THE ABOVE CONFIG IS ALL RIGHT?
QUESTION:
1 THE dai0-pin08 is need extra config in hardware ? need a resistance or something?
2 the sport3B need extra config in coding?
GenevaCooper - Moved from How to Use EngineerZone to ADSP-2156x. Post date updated from Thursday, December 21, 2023 to Friday, December 22, 2023 to reflect the move.
GenevaCooper - Moved from How to Use EngineerZone to ADSP-2156x. Post date updated from Friday, December 22, 2023 to Friday, December 22, 2023 to reflect the move.
Hi,
There is an example code for SPDIF in ADSP-21569 BSP, could you please refer that code for SPDIF configuration which may helpful for your application. Please find the BSP link below
download.analog.com/.../ADI_EV-2156x_EZ-KIT-Rel1.0.1.exe
Path: \Analog Devices\EV-2156x_EZ-KIT-Rel1.0.1\EV-2156x_EZ-KIT\Examples\drivers\adc\SPDIF_ASRC_DAC_AudioPassthrough
Also, for further assistance, please explain more about what issue you're facing ?
Regards,
Divya.P
so what should i do to address this issue (the output left channel audio with noise,and right channel audio is worse than left channel audio)
so what should i do to address this issue (the output left channel audio with noise,and right channel audio is worse than left channel audio)
Hi,
From the given configuration, seems you are using the same PCG (PCG_Device_B) to provide clock for both SPDIF_TX_CLK and SPDIF_TX_HFCLK. As shown in the image HFCLK should be 256xFS ,it should not be the same as SPDIF_TX_CLK. So please configure the HCLK as per the below condition and try configuring with different PCGs for each clock.

Please refer the below application note which discusses briefly about SPDIF,
https://www.analog.com/media/en/technical-documentation/application-notes/ee.266.rev.2.08.07.pdf
Also, Are you using 16 bit Data or 32 bit Data could you please confirm this?
Regards,
Divya.P
thank for your reply
but the issue(the output left channel audio with noise,and right channel audio is worse than left channel audio) is still exist。
1 the next is my update setting:



pcg B clk:3.072MHz
pcg A clk:12.288MHz
pcg B FS:48KHZ
2. adi_sport_ConfigData.nWordLength only in 23 or 24,the device can record audio( with noise).
3 how to set an right value about adi_sport_ConfigClock.nClockRatio and adi_sport_ConfigFrameSync.nFsDivisor , and what other sport api should be set exclude adi_sport_ConfigMC ,adi_sport_SelectChannel,adi_sport_ConfigClock ,adi_sport_ConfigData
4 some thing meke me confused when adi_sport_Open.ADI_SPORT_MODE is ADI_SPORT_MC_MODE , the device can record audio( with noise).
5 i only ste the api about spdif TX that adi_spdif_Tx_Open and adi_spdif_Tx_Enable, what other spdif tx api should be set?
Finally, do you have any other contact information? I want to resolve this issue quickly. Thank you
32 bit data
please give me some advices to deal with this issue ,thx
Hi,
Apologies for the delay.
We are working on this, will get back to you as soon as possible.
Regards,
Divya.P
look forwork to your reply ,thx