About EV-21569x_EZ-KIT-Rel1.0.1 Examples Audio_Passthrouth_I2S

I hope someone can help me,thanks.

Hi,

In the BSP example code 2 ADC (L&R channel data) input is given to 2 DAC (L&R channel data). We have modified the example for single ADC (left channel) input to 2 DAC outputs (left and right channel). See the attached example.

Here we enabled the single ADC by setting 0x31 in the Serial Port and Block Power Register (BLOCK_POWER_SAI).

If this doesn't meet your requirement, please explain your query in detail with a block diagram to assist you better.
 
Audio_Passthrough_I2S.zip
Regards,
Divya.P

Hello, maybe I didn't accurately describe the problems I encountered. I'm sorry. Let me redescribe my problem.I have attached my code please help me to modify it, I want to accept the data in int_SP0ABuffer10 to int_SP0ABuffer1 and int_SP0ABuffer2 and int_SP0ABuffer7 and int_SP0ABuffer8. I wonder how to do it?

ADI_CACHE_ALIGN int int_SP0ABuffer1[COUNT];	// DAC1
ADI_CACHE_ALIGN int int_SP0ABuffer2[COUNT];	// DAC2

ADI_CACHE_ALIGN int int_SP0ABuffer7[COUNT];	// DAC3
ADI_CACHE_ALIGN int int_SP0ABuffer8[COUNT];	// DAC4

ADI_CACHE_ALIGN int int_SP0ABuffer9[COUNT];	// ADC3
ADI_CACHE_ALIGN int int_SP0ABuffer10[COUNT];// ADC4

ADI_CACHE_ALIGN int int_SP0ABuffer4[COUNT];	// ADC1
ADI_CACHE_ALIGN int int_SP0ABuffer5[COUNT];	// ADC2

/* Destination Sport PDMA list */
ADI_PDMA_DESC_LIST iDESC_LIST_1_SP4A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP4A;

ADI_PDMA_DESC_LIST iDESC_LIST_1_SP5A;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP5A;

/* Source Sport PDMA list */
ADI_PDMA_DESC_LIST iSRC_LIST_1_SP4B;
ADI_PDMA_DESC_LIST iSRC_LIST_2_SP4B;

ADI_PDMA_DESC_LIST iDESC_LIST_1_SP5B;
ADI_PDMA_DESC_LIST iDESC_LIST_2_SP5B;

/* Memory required for SPORT */
static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory4B[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory5A[ADI_SPORT_MEMORY_SIZE];
static uint8_t SPORTMemory5B[ADI_SPORT_MEMORY_SIZE];

/* SPORT Handle */
static ADI_SPORT_HANDLE hSPORTDev4ATx;//TX DAC12
static ADI_SPORT_HANDLE hSPORTDev5ATx;//TX DAC34

static ADI_SPORT_HANDLE hSPORTDev4BRx;//RX ADC12
static ADI_SPORT_HANDLE hSPORTDev5BRx;//RX ADC34

void SPORTCallback(
    void        *pAppHandle,
    uint32_t     nEvent,
    void        *pArg
)
{
//	int i;
	int i,j;
	ADI_SPORT_RESULT eResult;
    /* CASEOF (event type) */
    switch (nEvent)
    {
        /* CASE (buffer processed) */
        case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED:
//			CallbackCount +=1;
//			if(CallbackCount==1)
//			{
//				Audio_Processing_Input(int_SP0ABuffer9,Mixdata[0].Mixer_input,float_Block.Rx_L1,float_Block.Rx_L11,0,Delay_BUFF1);
//				Audio_Processing_Input(int_SP0ABuffer9,Mixdata[1].Mixer_input,float_Block.Rx_L2,float_Block.Rx_L22,2,Delay_BUFF3);
//			}
//			if(CallbackCount==2)
//			{
//				Audio_Processing_Input(int_SP0ABuffer10,Mixdata[2].Mixer_input,float_Block.Rx_R1,float_Block.Rx_R11,1,Delay_BUFF2);
//				Audio_Processing_Input(int_SP0ABuffer10,Mixdata[3].Mixer_input,float_Block.Rx_R2,float_Block.Rx_R22,3,Delay_BUFF4);
//
//				CallbackCount=0;
//			}
			break;
        default:
        	 break;
    }
    /* return */
}
void PrepareDescriptors (void)
{

		iDESC_LIST_1_SP4A.pStartAddr	= (int *)int_SP0ABuffer1;
		iDESC_LIST_1_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_1_SP4A.XCount		= COUNT;
		iDESC_LIST_1_SP4A.XModify		= 4;
		iDESC_LIST_1_SP4A.YCount		= 0;
		iDESC_LIST_1_SP4A.YModify		= 0;
		iDESC_LIST_1_SP4A.pNxtDscp		= &iDESC_LIST_2_SP4A;

		iDESC_LIST_2_SP4A.pStartAddr	= (int *)int_SP0ABuffer2;
		iDESC_LIST_2_SP4A.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_2_SP4A.XCount		= COUNT;
		iDESC_LIST_2_SP4A.XModify		= 4;
		iDESC_LIST_2_SP4A.YCount		= 0;
		iDESC_LIST_2_SP4A.YModify		= 0;
		iDESC_LIST_2_SP4A.pNxtDscp		= &iDESC_LIST_1_SP4A;

		iDESC_LIST_1_SP5A.pStartAddr	= (int *)int_SP0ABuffer7;
		iDESC_LIST_1_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_1_SP5A.XCount		= COUNT;
		iDESC_LIST_1_SP5A.XModify		= 4;
		iDESC_LIST_1_SP5A.YCount		= 0;
		iDESC_LIST_1_SP5A.YModify		= 0;
		iDESC_LIST_1_SP5A.pNxtDscp		= &iDESC_LIST_2_SP5A;

		iDESC_LIST_2_SP5A.pStartAddr	= (int *)int_SP0ABuffer8;
		iDESC_LIST_2_SP5A.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_2_SP5A.XCount		= COUNT;
		iDESC_LIST_2_SP5A.XModify		= 4;
		iDESC_LIST_2_SP5A.YCount		= 0;
		iDESC_LIST_2_SP5A.YModify		= 0;
		iDESC_LIST_2_SP5A.pNxtDscp		= &iDESC_LIST_1_SP5A;

	//--------------------------------------------------------------------//
		iDESC_LIST_1_SP5B.pStartAddr	= (int *)int_SP0ABuffer4;
		iDESC_LIST_1_SP5B.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_1_SP5B.XCount		= COUNT;
		iDESC_LIST_1_SP5B.XModify		= 4;
		iDESC_LIST_1_SP5B.YCount		= 0;
		iDESC_LIST_1_SP5B.YModify		= 0;
		iDESC_LIST_1_SP5B.pNxtDscp		= &iDESC_LIST_2_SP5B;

		iDESC_LIST_2_SP5B.pStartAddr	= (int *)int_SP0ABuffer5;
		iDESC_LIST_2_SP5B.Config		= ENUM_DMA_CFG_XCNT_INT ;
		iDESC_LIST_2_SP5B.XCount		= COUNT;
		iDESC_LIST_2_SP5B.XModify		= 4;
		iDESC_LIST_2_SP5B.YCount		= 0;
		iDESC_LIST_2_SP5B.YModify		= 0;
		iDESC_LIST_2_SP5B.pNxtDscp		= &iDESC_LIST_1_SP5B;

		iSRC_LIST_1_SP4B.pStartAddr		=(int *)int_SP0ABuffer9;
		iSRC_LIST_1_SP4B.Config			= ENUM_DMA_CFG_XCNT_INT ;
		iSRC_LIST_1_SP4B.XCount			= COUNT;
		iSRC_LIST_1_SP4B.XModify		= 4;
		iSRC_LIST_1_SP4B.YCount			= 0;
		iSRC_LIST_1_SP4B.YModify		= 0;
		iSRC_LIST_1_SP4B.pNxtDscp		= &iSRC_LIST_2_SP4B;

		iSRC_LIST_2_SP4B.pStartAddr		=(int *)int_SP0ABuffer10;
		iSRC_LIST_2_SP4B.Config			= ENUM_DMA_CFG_XCNT_INT;
		iSRC_LIST_2_SP4B.XCount			= COUNT;
		iSRC_LIST_2_SP4B.XModify		= 4;
		iSRC_LIST_2_SP4B.YCount			= 0;
		iSRC_LIST_2_SP4B.YModify		= 0;
		iSRC_LIST_2_SP4B.pNxtDscp		= &iSRC_LIST_1_SP4B;

}

int Sport_Init(void)
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

	/* Open the SPORT Device 4A */
	eResult = adi_sport_Open(SPORT_DEVICE_4A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_I2S_MODE, SPORTMemory4A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 5A */
	eResult = adi_sport_Open(SPORT_DEVICE_5A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_TX, ADI_SPORT_I2S_MODE, SPORTMemory5A,ADI_SPORT_MEMORY_SIZE,&hSPORTDev5ATx);
	CHECK_RESULT(eResult);

	/* Open the SPORT Device 5B */
	eResult = adi_sport_Open(SPORT_DEVICE_5B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory5B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev5BRx);
	CHECK_RESULT(eResult);
	/* Open the SPORT Device 4B*/
	eResult = adi_sport_Open(SPORT_DEVICE_4B,ADI_HALF_SPORT_B,ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE, SPORTMemory4B,ADI_SPORT_MEMORY_SIZE,&hSPORTDev4BRx);
	CHECK_RESULT(eResult);

	/* Prepare descriptors */
	PrepareDescriptors();

	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4BRx,&iSRC_LIST_1_SP4B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Rx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev5BRx,&iDESC_LIST_1_SP5B,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev4ATx,&iDESC_LIST_1_SP4A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);
	/* Submit the first buffer for Tx.  */
	eResult = adi_sport_DMATransfer(hSPORTDev5ATx,&iDESC_LIST_1_SP5A,(DMA_NUM_DESC),ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM);
	CHECK_RESULT(eResult);

	/* Register SPORT Callback function */
	eResult = adi_sport_RegisterCallback(hSPORTDev4BRx,SPORTCallback,NULL);
	CHECK_RESULT(eResult);

	/*Enable the Sport Device 4B */
	eResult = adi_sport_Enable(hSPORTDev4BRx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 4A */
	eResult = adi_sport_Enable(hSPORTDev4ATx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 5A */
	eResult = adi_sport_Enable(hSPORTDev5ATx,true);
	CHECK_RESULT(eResult);
	/*Enable the Sport Device 5B */
	eResult = adi_sport_Enable(hSPORTDev5BRx,true);
	CHECK_RESULT(eResult);

	return eResult;

}

int Sport_Stop(void)
{
    /* SPORT return code */
    ADI_SPORT_RESULT    eResult;

    /*Stop the DMA transfer of  Sport Device 4B */
	eResult = adi_sport_StopDMATransfer(hSPORTDev4BRx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 4A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 5A */
	eResult = adi_sport_StopDMATransfer(hSPORTDev5ATx);
	CHECK_RESULT(eResult);
	/*Stop the DMA transfer of  Sport Device 5B */
	eResult = adi_sport_StopDMATransfer(hSPORTDev5BRx);
	CHECK_RESULT(eResult);
//--------------------------------------------------------//
	/*Close Sport Device 4B */
	eResult = adi_sport_Close(hSPORTDev4BRx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 4A */
	eResult = adi_sport_Close(hSPORTDev4ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 5A */
	eResult = adi_sport_Close(hSPORTDev5ATx);
	CHECK_RESULT(eResult);
	/*Close Sport Device 5B */
	eResult = adi_sport_Close(hSPORTDev5BRx);
	CHECK_RESULT(eResult);

	return eResult;
}

This is the equivalent of an audio routing function, routing a certain input data to any output. I am achievable on 21489. But this operation cannot be realized on the DMA of 21569, please help solve this problem thank you!

Hello, I have solved the question I asked before. Now I find a new problem with the new routine you gave, which is that the delay difference between the two outputs is 0.01ms, the 96K sampling rate I use. How can I equal the delay of the two outputs?But I do not have this lag difference with the I2S original routine. Please help me solve this problem thank you!

Hi ,

Apologies for the delay in response.

Please see the attached code for inputting from a single ADC (left channel) and outputting to two DACs (left and right channels).  We haven't observed any delay with this implementation.

Please let us know if you need any further assistance.

2335.Audio_Passthrough_I2S.zip

Regards,
Ranjitha R