MMR access time variation

Hi Christian,

Unlike previous SHARC processors, the latest SHARC+ processors can have higher MMR access latencies. This is mainly due to the interconnect fabric between the core and the MMR space, and also due to the number of different clock domains (SYSCLK, SCLK0, SCLK1, DCLK and CAN clock).

All MMR accesses are through SCB0, which is in the SYSCLK domain, while peripherals are in the SCLK0/1, SYSCLK, and DCLK domains.

Please refer "System MMR Latencies" in the app note EE-412.  This app note discussed about the measurement of MMR latency in core cycles for different peripherals

Please refer the below link for EE-412
www.analog.com/.../ee412v02.pdf

Regards,
Divya.P

Hi Divya,

thank you.
I already saw this app note, seems I missed that table.

But isn't there a way to optimize for or avoid those latencies?
Especially for GPI that I read every audio sample from e.g. the REG_PORTA_DATA register.
If this takes me ~80 CCLK cycles every sample that's a huge increase compared to older SHARCs.

Regards
Christian

Hi Christian,

As we already mentioned, latest SHARC+ processors can have higher MMR access latencies due to the interconnect fabric between the core and the MMR space, and also due to the number of different clock domains

Please refer the same Optimization App note which has techniques for reduce the latency.

Also, we suggest you to refer the App note EE-408 for Using ADSP-2156x High Performance FIR/IIR Accelerators from the below link.
www.analog.com/.../EE408V02.pdf
www.analog.com/.../EE408V02.zip

The ADSP-2156x FIRA performance is around 4.44x the ADSP-214xx FIRA performance. This increase is because the ADSP-2156x FIRA runs at CCLK (1 GHz), whereas the ADSP-214xx FIRA
runs at PCLK, which is a maximum of CCLK/2 (225 MHz)

Regards,
Divya.P