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ADSP-21565 Hardware Reference Related Question

Category: Datasheet/Specs

Hi 

I am reading the ADSP-21565 hardware reference document as given in the following link:

ADSP-2156x SHARC+ Processor Hardware Reference (analog.com)

In page 18-12 (pg796), the document introduces the "Width Capture Mode Overflow" related things.

The document gives the following description:

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If the timer overflows and the TIMER_TMR[n]_CFG.TMODE bit =b#1010, the TIMER_TMR[n]_PER and TIMER_TMR[n]_WID registers are not updated. If the timer overflows and the TIMER_TMR[n]_CFG.TMODE bit =b#1011, the TIMER_TMR[n]_PER and TIMER_TMR[n]_WID registers are updated only if a trailing edge is detected at a previous measurement report.

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And then the document gives Figure 18-6 and Figure 18-7 to help understanding.

But it seems the titles of Figure 18-6 and Figure 18-7 are reversed.

Figure 18-6 seems to describe the TMR_CFG.TMODE=b#1011 but the tilte writes "Figure 18-6: Example Timing for Width Capture Followed by Period Overflow (TMR_CFG.TMODE=b#1010)".

And Figure 18-7 seems to describe the TMR_CFG.TMODE=b#1010 but the title writes "Figure 18-7: Example Timing for Width Capture Followed by Period Overflow (TMR_CFG.TMODE=b#1011".

Could you please double confirm?

Thanks,

Tingting.

  • By the way, the description in  Pg 18-52 (Trigger Slave Enable Register) seems also not correct.

    1. As a trigger slave, each timer can generate a unique data trigger pulse signal. 

    Tirgger slave   ->  generate a unique data trigger pulse signal????

    2.  The reset value of the TIMER_TRG_IE register is 0xFFFF, masking these triggers after reset.

    In the picture, the reset value is 0x0000 not 0xFFFF described in the text.

    Could you please help to double confirm?

  • Hi Tingting,

    In both images, As per the HRM, when the TIMER_TMR[n]_CNT register wraps around from 0xFFFF FFFF to 0, a timer status interrupt request (when enabled) is generated. At this point Status Interrupt Latch bit set and error type status bits change to indicate a count overflow due to a period greater than the range of the counter. This indication is referred to as an error report.

    When error report occurred, the TIMER_TMR[n]_CFG.TMODE bit =b#1010, the period and width registers are registers are never updated. (please refer img 1010-timer).

    If the timer error report occured and the TIMER_TMR[n]_CFG.TMODE bit =b#1011, the period and width registers are updated only if a trailing edge is detected at a previous measurement report. (please refer img b#1011).

    Then could please explain how the above images are swapped.

    Regarding"2nd  question"
    >>> We will fix in future, Thank you for pointing out.

    Regards,565132.zip
    Divya.P

  • Hi Divya,

    I am still confused. Let's check the question from another point.

    Let's compare the Figure 18-4 and Figure 18-7.

    1. TMODE is the same = b#1011

    2. Check the situation when PULSE_HI = 1.

    we can see the following difference.

    • Measurement report happens when a falling edge is detected in Figure 18-4;
    • But Measurement report happens when a rising edge is detected in Figure 18-7.

    It seems not logical?

    Thanks,

    Tingting.

  • Hi,

    Figure 18-4 explains about how the Example of Width Capture Deasserted Mode (TMODE=b#1011) works.  As mentioned in your image When the TIMER_TMR[n]_CFG.TMODE bit=b#1011 set, the measurement report occurs just after the width buffer register captures its value at a falling edge.

    But Figure 18-7 explains about the Example Timing for Width Capture Followed by Period Overflow (TMR_CFG.TMODE=b#1011). The measurement report is not only depend on the trailing edge but also width buffer register. So, here once the width buffer register updates its value, error reporting is occurred at rising edge, because of the over flow error.

    Regards,
    Divya.P