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what's default samplerate of Audio_Loopback_TDM in cces for EV-21569-EZKIT

Category: Software
Product Number: EV-21569-EZKIT
Software Version: cces2.11.0

Hi,

I want to know that what's default samplerate of Audio_Loopback_TDM  in cces for EV-21569-EZKIT? and I want to know that Mapping relations of int_SP0ABuffer1, int_SP0ABuffer2 and audio output channels?

BestRegards!

Ruizhang

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  • Hi RuiZhang,

    Sample rates are divided down from the master clock (MCLK) input. On the EV-21569-EZKIT, the MCLKI to the CODEC is fixed to the 24.576Mhz source. If you program the PLL of ADAU1962A with either 128 x fs, 192 x fs, 256 × FS, 384 × FS,  512 x FS or 768 x FS. You can observe that the audio output is perfect at all the sampling rate (32KHz, 48KHz , 64KHz, 96KHz, 128KHz and 192KHz) of CODEC. In Audio_Loopback_TDM example code, the default sample rate is 48KHz.

     In "Audio_Loopback_TDM" example project, int_SP0ABuffer1, int_SP0ABuffer2,  int_SP0ABuffer4 and int_SP0ABuffer5 are user defined buffers. The input data is received from ADC is written to int_SP0ABuffer4 and int_SP0ABuffer5 buffer using SPORT4B.

     The data in int_SP0ABuffer4 buffer is copied to int_SP0ABuffer1 buffer and data in int_SP0ABuffer5 buffer is copied to int_SP0ABuffer2 buffer. ADAU1979 has only 4 ADC, so in example code 4 channel input data is copied to 8 channel DAC output, you can see it in sport callback in source code. Then the copied data( int_SP0ABuffer1, int_SP0ABuffer2) is transmitted to DAC using SPORT4A.

    Regards,
    Divya P

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  • Hi RuiZhang,

    Sample rates are divided down from the master clock (MCLK) input. On the EV-21569-EZKIT, the MCLKI to the CODEC is fixed to the 24.576Mhz source. If you program the PLL of ADAU1962A with either 128 x fs, 192 x fs, 256 × FS, 384 × FS,  512 x FS or 768 x FS. You can observe that the audio output is perfect at all the sampling rate (32KHz, 48KHz , 64KHz, 96KHz, 128KHz and 192KHz) of CODEC. In Audio_Loopback_TDM example code, the default sample rate is 48KHz.

     In "Audio_Loopback_TDM" example project, int_SP0ABuffer1, int_SP0ABuffer2,  int_SP0ABuffer4 and int_SP0ABuffer5 are user defined buffers. The input data is received from ADC is written to int_SP0ABuffer4 and int_SP0ABuffer5 buffer using SPORT4B.

     The data in int_SP0ABuffer4 buffer is copied to int_SP0ABuffer1 buffer and data in int_SP0ABuffer5 buffer is copied to int_SP0ABuffer2 buffer. ADAU1979 has only 4 ADC, so in example code 4 channel input data is copied to 8 channel DAC output, you can see it in sport callback in source code. Then the copied data( int_SP0ABuffer1, int_SP0ABuffer2) is transmitted to DAC using SPORT4A.

    Regards,
    Divya P

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