Category: Hardware
Product Number: ADSP21569
Hello,
we are trying to replace our ADSP21469 module with a pin compatible ADSP21569 module. We now face the problem, that the module is used in a couple of
different devices each using the pins a bit differently. Because the 20 PIN DAI of the 469 got pin-reduced and duplicated to two DAIs with 14 pins, we need to partition the signals onto two DAIs.
I have a couple of questions:
- Is there a difference between taking a clock signal directly:
PCGA_CLK_O to SPORTx_CLK_I (only within on DAI)
or going through the pin buffer:
PCG0_CLKA_O to DAI0_PBxx_I (DAI0_PBENxx_I = HIGH) and from DAI0_PBxx_O to SPORT0A..3B_CLK_I (DAI0) and
PCG0_CRS_CLKA_O to DAI1_PBxx_I (DAI1_PBENxx_I = HIGH) and from DAI1_PBxx_O to SPORT4A..7B_CLK_I (DAI1)
- The latter seems to enable usage of PCG clocks across DAIs using the PCG0_CRS_CLKx_O source, but I guess there will be a slight timing difference between the CLK edges on the different ways? Is there anything else to pay attention to?
- For another usecase a further indirection is possible when passing the SPDIF recovered clock SPDIF0_RX_CLK_O through a PCG0_EXT_CLK0_I (Bypassmode) and then again distributing it to both DAIs like above. Do you see any dangers here?
- In the 21569 Hardware Reference manual at the PCGs I can read this:
Cross Mode Connections
The symmetric dual DAI architecture allows cross connections between both PCGs (A,B) and (C,D) to the other DAI. Each PCG (A through D) supports an alternative input clock (PCG0_EXTx_I)(see Figure 24-1 PCG Block Diagram) which can be sourced via a DAI pin buffer from the other DAI. Note however if routing a source (clock or FS) only DAI pin buffer 2 to 20 can be used (DAI pin buffer 1 is no longer available and is replaced by the DAI CRS buffer for the other DAI). See DAI Routing Capabilities for more information.
Looking at the "DAI Routing Capabilities" Table in the same manual, I cannot see that the cited is possible. The SRU-Plugin for CCES doesn't let me configure this neither.
Is this an error in the manual or can you explain me how to achieve sourcing any DAIx pin buffer to PCG_EXTx_I?
Kind regards,
Stefan
