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Questions regarding ADSP-21569 SOM

Category: Hardware
Product Number: ADSP-21569
Software Version: -

Hello,

I have some questions regarding the datasheet of the ADSP-21569 and the Reference Design EV-21569-SOM.

1: The Pins L6 and K6 are labeled VDD_PLL in the EV-21569-SOM Schematic (REV A and Rev B) while these Pins are labelled as VDD_INT in the Datasheet (Rev B).

    Is it necessary to add an additional filter to separate these Pins from the rest of the VDD_INT supply? Are these 2 Pins for the supply of the PLL?

2: Pin G19 DMC0_RZQ should be connected to GND with a 34 Ohm resistor.

  Is there any experience if a 33 Ohm resistor is also working? There is only a small variety of 34 Ohm resistors and therefore parts in stock are rare.

3. Pin B12 DMC0_RST#: is the termination with 100 Ohm of that signal necessary? There is also a 10k Ohm pull-up resistor to 1,35V which seems useless considering the 100 Ohm resistor to VTT.

4. Is the termination resistor between DMC0_CK and DMC0_CK# with the value of 200 Ohm correct? I would have thought that you use a 100 Ohm termination resistor for a differential pair with a characteristic impedance of 100 Ohm.  

5. Do you have some further informations about the Prepregs that are used in the stackup of the PCB EV-21569-SOM?

6. Do you know if the EV-21569-SOM has any issues regarding Signal Integrity or EMI?

  • Hi Stephan,

    Regarding Quest 1: You can connect the pins Pins L6 and K6 directly to VDD_INT supply.

    Regarding Quest 2: This pin used for external calibration. So, 34 Ω external pull-down must be added to this pin.

    Regarding Quest 3: One pull-up is enough for this pin. For Evaluation purpose implemented this option.

    Regarding Quest 4: Please refer the App note EE-418 ADSP-2156x Board Design Guidelines for Dynamic Memory Controller for DDR_CLK termination from the below link,
     www.analog.com/.../ee418v02.pdf

    Regarding Quest 5&6: We will check and update you.
     
    Regards,
    Anand Selvaraj.

     

  • Hello Anand,

    thanks for your answers so far. I hope you can answer the rest of my questions as soon as posible.

    I thought about Question 3 again:

    If the DDR3 Reset Output on the DSP is a push-pull output than it could be useful to also terminate the signal if rise- and fall-times are in the same range as that of the high-speed DDR3 signals to avoid reflections on that trace.

    Best regards,

    Stephan