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Product Number: ADSP21565
Software Version: NONE
Question 1: if the sys of DSP slave_ Clkin0 uses external crystal instead of sys of DSP master_ Clkout, is there a problem that two DSPs are not synchronized?
Question 2: after the customer connected the pin10 of the DSP master to the DSP slave pin5, the test found that the levels of pin10 and pin5 were not consistent, so it was poured back to VDD_ ANA and VDD_ CLK。 Cause VDD_ ANA and VDD_ The voltage of CLK rises from 1.8V to 2.0V. Is the pin10 of the DSP master unable to connect to the DSP slave pin5?
