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SCLK0 divisor in 21565


For some reason, I need to config SCLK0 to 98.304MHz as the CLKIN0 is 24.576MHz.

I want to set CCLK to be 983.04Hz and SYSCLK to be 491.52MHz, then make SCLK0 divisor as 5 to get 98.304MHz. 

What confused me is that in the 21565 datasheet, I see the SCLK0 divisor must be 2 or 4 or 6 from SYSCLK, to make SYSCLK small than 500MHz, I can only use 4 as divisor. So the SYSCLK is 393.216MHz and CCLK is 786.432MHz which is much less than 1GHz.


However in the Hardware Reference, it described that the S0SEL can be set between 1 and 7.


So, can I use 5 to make the core run at max frequence as well as SCLK0 to be 98.304MHz?