No. Event numbers that are not listed in the PMU events table (refer to the Cortex‑A55 Technical Reference Manual (TRM) ) are reserved and must not be used.
Yes, ADSP-SC84x IIR accelerators have support for IIR coefficient slewing feature. For more information, please refer to Hardware Reference Manual of ADSP-SC84x processor.
If a frame sync divisor is greater than 1, the PCG frame sync output frequency is equal to the input clock frequency, divided by a 20-bit integer. This integer is specified in the PCG_CTLA0.FSDIV/PCG_CTLB0…
For EL0, EL1, and EL2, the security state is determined by the SCR_EL3.NS bit. EL3 always operates in the Secure state. When SCR_EL3.NS = 1, the processor is in the Non-secure state. When SCR_EL3.NS =…
PKA operands are written to a dedicated operand RAM accessible through memory-mapped registers. Software writes operands A, B, and modulus N to designated offsets in this internal SRAM before issuing an…
The PKIC generates separate interrupt outputs per core cluster:
Cortex-A55 : Routed through the GIC as an SPI
SHARC-FX : Routed through the SEC
HSM subsystem : Internal to the HSM
When a PMU interrupt condition occurs, the core asserts nPMUIRQ. This signal is routed to an external interrupt controller for masking and prioritization and is also provided to the CTI as a trigger input…