ADSP-21065L Memory DMA

I am supporting a legacy product that is using the 21065L.  I would like to replace a memcpy() with a DMA copy to improve the throughput.

The original code is:

UNSIGNED32 *extMem = 0x10000000;

UNSIGNED32 *intMem = 0x0000D000;

memcpy(extMem, intMem, 100);

The DMA code is:

    // DMA off
    *pDMAC1 = 0;


    // set DMA control regs
    *pIIEP1 = (UNSIGNED32)(intMem); // internal RAM     
    *pIMEP1 = 1; // single increment
    *pCEP1 = 100; // count
    *pEIEP1 = (UNSIGNED32)(extMem); // external RAM
    *pEMEP1 = 1; // single increment
    *pECEP1 = 100; // count


    // turn DMA on
    *pDMAC1 = (DEN | TRAN | MASTER);


    // wait for DMA to finish, to keep the same flow as with memcpy
    while ((*pDMASTAT & DMA7ST) != 0);  

When I run this, nothing happens.  It doesn't hang, it just falls through with no memory writes at all.

I'm sure it's something simple, as I'm not familiar with this device.

TIA.

Parents
  • Thanks for the quick response.

    Your answer doesn't explain why the DMA transfer never gets started.  I am monitoring the Ext RAM Write Enable signal, and there is no activity.  Using the interrupt would work to determine when the transfer is complete, as would monitoring the interrupt flag.

    Also, per def21065L.h, the Ext DMA channels are 6 and 7.

    /* DMA Channel Status (DMASTAT) */

    #define

    DMA0ST BIT_0 /* DMA channel 0 (SPORT0_A RX) Active Status */

    #define

    DMA1ST BIT_1 /* DMA channel 1 (SPORT1_A RX) Active Status */

    #define

    DMA2ST BIT_2 /* DMA channel 2 (SPORT0_A TX) Active Status */

    #define

    DMA3ST BIT_3 /* DMA channel 3 (SPORT1_A TX) Active Status */

    #define

    DMA4ST BIT_4 /* DMA channel 4 (SPORT0_B RX) Active Status */

    #define

    DMA5ST BIT_5 /* DMA channel 5 (SPORT1_B RX) Active Status */

    #define

    DMA6ST BIT_6 /* DMA channel 6 (EPB0) Active Status */

    #define

    DMA7ST BIT_7 /* DMA channel 7 (EPB1) Active Status */

    #define

    DMA8ST BIT_8 /* DMA channel 8 (SPORT0_B TX) Active Status */

    #define

    DMA9ST BIT_9 /* DMA channel 9 (SPORT1_B TX) Active Status */

     

    Please advise.

Reply
  • Thanks for the quick response.

    Your answer doesn't explain why the DMA transfer never gets started.  I am monitoring the Ext RAM Write Enable signal, and there is no activity.  Using the interrupt would work to determine when the transfer is complete, as would monitoring the interrupt flag.

    Also, per def21065L.h, the Ext DMA channels are 6 and 7.

    /* DMA Channel Status (DMASTAT) */

    #define

    DMA0ST BIT_0 /* DMA channel 0 (SPORT0_A RX) Active Status */

    #define

    DMA1ST BIT_1 /* DMA channel 1 (SPORT1_A RX) Active Status */

    #define

    DMA2ST BIT_2 /* DMA channel 2 (SPORT0_A TX) Active Status */

    #define

    DMA3ST BIT_3 /* DMA channel 3 (SPORT1_A TX) Active Status */

    #define

    DMA4ST BIT_4 /* DMA channel 4 (SPORT0_B RX) Active Status */

    #define

    DMA5ST BIT_5 /* DMA channel 5 (SPORT1_B RX) Active Status */

    #define

    DMA6ST BIT_6 /* DMA channel 6 (EPB0) Active Status */

    #define

    DMA7ST BIT_7 /* DMA channel 7 (EPB1) Active Status */

    #define

    DMA8ST BIT_8 /* DMA channel 8 (SPORT0_B TX) Active Status */

    #define

    DMA9ST BIT_9 /* DMA channel 9 (SPORT1_B TX) Active Status */

     

    Please advise.

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