Problem with TS101 in emulation mode

Hello all,

I have a problem with ADSP-TS101S DSP (on ADDS-TS101S-EZLITE board): after EMUTRAP instruction is loaded through JTAG, DSP goes into emulation mode (EMUMOD bit in EMUSTAT register is set), but IRFREE bit in EMUSTAT register does not become 1, so that it would be possible to insert instructions through emulator.
I am not using ADI emulator, but a different tool to access DSP through JTAG.
The sequence of JTAG operations performed:
1. DSP comes out of power-on-reset
2. TRST signal is asserted for 1ms, then deasserted
3. EMUCTL JTAG scanchain is selected, EMUCTL register set to value 1 (EMEN bit set)
4. EMUTRAP JTAG instruction is loaded
5. EMUSTAT JTAG scanchain is selected, EMUSTAT value is read. Data that is shifted out of DSP: 0xFFFFFFFD
Under which conditions must IRFREE bit become 1?
Best regards,
Konstantin.
  • 0
    •  Analog Employees 
    on Feb 17, 2011 4:47 AM

    Hi Konstantin,

              We have limited support for debugging the JTAG access related problem with different tools other than ADI. I could only see that this details are available under the "Debug Functionality" chapter on ADSP-TS101 HRM. Based on the information from the HRM, the IRFREE bit is set by default. In your code I am not sure why this bit is not set.  Also refer the below information on the ADSP-TS101 HRM on page 342:

    Whenever the TigerSHARC processor is in emulation mode and ready for a new instruction line driven into the EMUIR  register, the EMU pin is driven low until such an instruction is inserted.

     

    In your system, have you checked the EMU pin status to see what happens?

     

    Best Regards,

    Jeyanthi

     

     

     

  • 0
    •  Analog Employees 
    on Feb 17, 2011 5:32 AM

    Hi Konstantin,

                   Thanks for the feedback. Since the EMU# pin is the output from processor which is used by the  Emulator or any other JTAG tool, I feel this is implicit that the EMUOE bit need to be set in the code. I will also make sure that this is explicitly added to the documentation.

    Best Regards,

    Jeyanthi

  • Hi Jeyanthi,

    Thank you for your reply.

    The problem is already solved: EMUOE bit in EMUCTL register not only controls behavior of EMU pin, but also behaviour of IRFREE bit (however this is not mentioned in HRM). So, in order to make IRFREE bit show whether EMUIR is ready for new instruction, EMUOE bit has to be set.

    Best Regards,

    Konstantin

  • 0
    •  Analog Employees 
    on Apr 29, 2019 10:39 AM
    This question has been closed by the EZ team and is assumed answered.