I need to increase the WRL pulse width to match the other peripheral device criteria.....
a) WRL width can be changed by increasing wait state ............maximum in TS 201 upto 3 wait cycle.
keeping fixed input crystal frequency (basically SCLK) how way i can increase the WRL pulse width ?
b) Any thing can be done using ACK signal ?
c) need to write some special instruction ?
Please somebody help me regarding this issue.
In my custom TS201 board one DAC (AD7538) required 240 nsc WR pulse , where i am not able to match this
using external crystal (SCLK) 32 MHz.
Thank you for technical support . YES !! Now my custom Tiger-sharc(TS201) board is working fine .
AD7538 , 14 bit DAC need 240 nsec where as TS201 processor generating maximum 145 nsec WRL pulse
even setting maximun WAIT state (three for TS201) by configured SYSCON reg using 32Mhz input clock frequency.
I am Trying to extend WRL pulse by applying ACK signal. But after applying generated ACK signal to the processor going to hang state.
MISTAKE WAS ..............Proper generation of ACK signal.
As per your suggestion
So my generated ACK signal was not match as per requirement.
But if ACK signal timing not matching processor going to hand state .
Finally Interface between TS201 and AD7538 working fine.