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How can increase the WRL after using max wait cycle.(for TS201)

AshokMajee
on Jun 8, 2012

I need to increase the WRL pulse width to match the other peripheral device criteria.....

a) WRL width can be changed by increasing wait state ............maximum in TS 201 upto 3 wait cycle.

keeping fixed input crystal frequency (basically SCLK) how way i can increase the WRL pulse width ?

b) Any thing can be done  using ACK signal ?

c) need to write some special instruction ?

Please somebody help me regarding this issue.

In my custom TS201 board one DAC (AD7538) required 240 nsc WR pulse , where i am not able to match this

using external crystal (SCLK) 32 MHz.

Regads

ASHOK

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  • 0 on Jun 15, 2012 4:29 PM

    Hello jeyanthi,

    Thank you for technical support . YES !! Now  my custom Tiger-sharc(TS201) board is  working fine .

    Problem :

       AD7538 , 14 bit DAC need 240 nsec where as TS201 processor generating maximum 145 nsec WRL pulse

    even setting maximun WAIT state (three for TS201) by configured SYSCON reg using 32Mhz input clock frequency.

    I am Trying to extend WRL pulse by applying ACK signal. But after applying generated  ACK signal  to the processor going to hang state.

    MISTAKE WAS ..............Proper generation of ACK signal.

    As per your suggestion

    "The external port accesses are extended when this signal is asserted low in
      middle of the external memory accesses."

    So my  generated ACK signal was not match as per requirement.

    But if ACK signal timing  not matching  processor going to hand state .

    Finally  Interface between TS201 and AD7538 working fine.

    Regards

    ASHOK

Reply
  • 0 on Jun 15, 2012 4:29 PM

    Hello jeyanthi,

    Thank you for technical support . YES !! Now  my custom Tiger-sharc(TS201) board is  working fine .

    Problem :

       AD7538 , 14 bit DAC need 240 nsec where as TS201 processor generating maximum 145 nsec WRL pulse

    even setting maximun WAIT state (three for TS201) by configured SYSCON reg using 32Mhz input clock frequency.

    I am Trying to extend WRL pulse by applying ACK signal. But after applying generated  ACK signal  to the processor going to hang state.

    MISTAKE WAS ..............Proper generation of ACK signal.

    As per your suggestion

    "The external port accesses are extended when this signal is asserted low in
      middle of the external memory accesses."

    So my  generated ACK signal was not match as per requirement.

    But if ACK signal timing  not matching  processor going to hand state .

    Finally  Interface between TS201 and AD7538 working fine.

    Regards

    ASHOK

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